New Features in SynaptiCAD Tool Suite V13.0
New Import/Export Features
WaveFormer Pro and DataSheet Pro have several new import and export formats
in addition to all the simulators and test equipment that are already supported.
- Supports import of binary TR0 files generated by HSPICE and OmegaSim.
- Supports export to the VCD file format.
- Supports import of Agilent MSO (mixed-signal oscilloscope) waveforms (.csv files).
- Extended VCD import now supports import of waveform data's input/output direction.
- Generation of Tri-state enable signals now recognizes "undriven" segments as a
tri-state condition for Agilent and Tektronix pattern generators.
- Increased speed of Verilog/VHDL testbench code generation.
Performance Enhancements to the Waveform Window
- We have improved the speed and drawing capabilities of the Waveform Window that
is used in all of our timing diagram editor and simulation products.
- Faster rendering of large digital waveform files.
- Faster analog waveform drawing.
- 10x increase in waveform compression ratio for repeating waveform patterns.
- Increased speed of waveform block copy with improved compression support.
General User-Interface Improvements
- Based primarily on user feature requests, we have added more graphical objects
and functions to the timing diagram editors and waveform window.
- The Search box on toolbar can now search waveforms for a user-specified extended
state value. The search begins on the first selected signal and searches left
to right, then searches the next signal.
- Standardized selection of signal names in timing diagram to use ctrl/shift keys for multiple selection.
- Pressing the key combo <ctrl>-a in the signal label window selects all signals in the diagram.
- Signal direction and position are shown in the label window as columns to the left of the signal name.
These columns can be disabled by choosing the Options > Drawing Preferences
menu and un-checking Show Indexand Show Signal Direction.
- The export state of the signal is shown by the color of the direction icons in the signal label window.
- Ellipses and rectangles can be placed in a diagram to highlight text or other areas of interest.
- Sort selected signals alphabetically by name with the the Edit > Sort Signals
By Name menu option. This will rearrange the order of the signals in the diagram.
- Markers can now display the state values for the signals at the marker time.
Double click on a marker to open the Marker Properties dialog and check the Display Signal States box.
- Rainbow signal coloring control in Drawing Preferences dialog.
- Global Find and Replace displays a count of the total replacements in the status bar at
the bottom of the main window.
- Expandable file browsing dialogs with support for filename auto-completion.
- USB keys are supported on Linux.
- The default location of new projects can be set by user.
- Timing Diagram Editor 4: Analog Signals shows how to create, edit, and view analog signals.
- Simulation 2: Using WaveFormer with ModelSim VHDL describes how to setup WaveFormer
to control the ModelSim simulators.
- Test Bench Generation 2: Reactive Test Bench Option shows the
basic steps for creating a single timing diagram test bench
that can respond to the model under test during simulation.
- Waveform Comparison Tutorial shows how to create compare waveforms and to
compare two separate diagrams.
- Transaction Tracker Tutorial explores semantic differences between some
of the most commonly used PSL operators and assertions statements.
- Gigawave and WaveViewer Viewer Tutorial explores the
waveform window from the perspective of viewing very large files
and finding information (rather than editing small files).
Simulation and Debugging Improvements
- BugHunter Pro is the graphical debugging environment that comes with
VeriLogger Extreme. BugHunter can also be purchased separately to work with other simulators.
- Doubled simulation speed when watching signals in the waveform window. See the BugHunter
and VeriLogger Manual Section 2.2: Watching Signals and Components for more information.
- Show current simulation time and current scope in status window.
- Support for displaying column location of errors in error window.
- Able to set one or more top level components to simulate in languages that support this
feature. See the BugHunter and VeriLogger Manual Step 6: Build the Project and Set
the Top for more information.
- Top-level instances can be specified using a VeriLogger Extreme scd_top command line option.
See the BugHunter and VeriLogger Manual Section 5.6 Simx Simulation Build Command Line
Options for more information. --scd_top [unitname]
- Signals and Variables that have changed state since last simulation step will
display with red values in the project tree and inspect window. See the BugHunter
and VeriLogger Manual Section 2.4 Inspect Values for more information.
- Compiled library files are shown in project window tree. See the BugHunter
and VeriLogger Manual Section 2.7 Using Component Libraries for more information.
- Included files displayed in project tree for each compiled source file. See the
BugHunter and VeriLogger Manual Section 4.2 Navigating Code with the Project
Window for more information.
- The simulator Command Console now stores separate command histories for
each simulator you use (since different simulators have different command sets that
can be used when a simulation is paused). See the BugHunter and VeriLogger Manual Section 2.6
Command Console for Interactive Debugging for more information.
- Toolbar controls added for navigating backwards and forwards through history of recently
visited source editor windows. See the BugHunter and VeriLogger Manual Section 4.3 Navigating
Code with Buttons and Report Tabs for more information.
- BugHunter now supports debugging and waveform capture with Synopsys VCS simulations.
See the BugHunter and VeriLogger Manual Step 1: Setup the Simulator Path for more information.
- Added support for running VHDL/Verilog bidirectional translators from GUI. See the BugHunter
and VeriLogger Manual Section 8.1: Setup Project for Translation for more information.
You will need a V2V license to use this feature.
- Project design hierarchy tree can expand into arrays and bit vectors and show values for
these. See the BugHunter and VeriLogger Manual Section 2.4 Inspect Values for more information.
New Features pages for previous versions:
List of Features in Version 12.0
List of Features in Version 11.0