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Objects and Types

Verilog has the following types defined:

• Register
• Net
• Integer, real and time variables

In VHDL, three classes of objects (Signal, Variable, Constant) are defined, each of which can be a scalar, composite, access or file type.

Verilog and VHDL are based on the same 4-level logic system (0,1,X,Z). Verilog2VHDL uses the IEEE standard 9-level std_ulogic type to translate the logic-levels in Verilog input.

Verilog2VHDLtranslates registers, integer, real and wire variables declared in Verilog to equivalent VHDL objects. For example, the basic Verilog data type wire is equivalent to the VHDL resolved type std_logic. Similarly, a vector in Verilog is equivalent to the VHDL resolved type std_logic_vector.

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