This chapter covers advanced simulation techniques that are useful when working with FPGA layout tools and FPGA encrypted models. First, VeriLogger Extreme supports SDF timing simulations. Most FPGA tools will generate an SDF timing file after placing a design and this chapter describes how to use the SDF timing during simulation. Also VeriLogger Extreme supports the two most common encrypted model support: Protected Envelopes from IEEE Standard 1364-2005 and the older SmartModel SWIFT standard.