If you are using the command line version of the translator, you can control the translator by adding command line arguments after listing the file(s) to be translated:

 verilog2vhdl input_file [output_file] [options] [-Help] 

                         [-Usage] [-Version]

where options can be a combination of:

[-Replace] [-Silent] [-No_Package] [-No_Extract_comments]

[-Environment {Mentor|Synopsys|Generic}] [-Package {HDL files}]

[-Log {logfile_name}] [-87|-93] [-No_Component_check]

[-Component_check] [-SYNTH] [-Map_Regs_to_Variables]

[-No_Synth] [-No_Zero_wait] [-Make_Defines_Constants] [-Make_Parameters_Constants]

[-Reserved_Identifier_Prefix {prefix string}] [-Reserved_Identifier_Suffix {suffix string}]

[-Preserve_Order] [-Verilog_PreProcessing] [-Architecture_Name] [-No_header]

Translation Option Summary

-Replace (-r):

Replace the existing output_file; default is to backup the output_file to <output_file>.old

-Silent (-s):

Supress printing out of messages indicating translator actions

-No_Package (-np):

Valid with the [-Package] option; suppresses writing out of VHDL packages of Verilog files supplied with [-Package] option; default is to create VHDL package with filename <pkgfilename_without_extension>_pack.hdl

-Environment {Mentor|Synopsys|Generic} (-e {m|s|g}):

Prints VHDL which is compliant with specified option, default is Generic

-Package {HDL files} (-p {HDL files}):

Loads the HDL files specified with this option into database

-Log {logfile_name} (-l {logfile name}):

Logs translator messages into file <logfile_name>; default log file is 'v2v.log'

-87:

Produces VHDL compatible with 1076-1987 compliant simulator

-No_Extract_comments (-ne):

Does not preserve comments in Verilog input

-No_Component_check (-ncc):

Does not look for module declarations for modules instantiated in instantiations. This is useful for translating designs which use large libraries

-SYNTH (-synth):

Produces synthesizable VHDL

-Map_Regs_to_Variables (-mrv):

Produces synthesizable VHDL with procedural assignments being mapped to variable assignments

-No_Zero_wait (-nz):

Does not print 'WAIT FOR 0 ns;' overridden by -synth option

-Make_Defines_Constants (-mdc):

Makes all `defines encountered in the input file constants in the Architecture; default is to create Generics in Entity

-Reserved_Identifier_Prefix <prefix string> (-rip <prefix string>):

Prefixes specified string to a reserved verilog2vhdl identifier. (See User's Manual, Chapter 3) for VHDL compliance

-Reserved_Identifier_Suffix <suffix string> (-ris <suffix string>):

Suffixes specified string to a reserved verilog2vhdl identifier. (See User's Manual, Chapter 3) for VHDL compliance

-Preserve_Order (-po):

When printing VHDL, retain the order of concurrent constructs in the Verilog input; default is to format the output VHDL

-Verilog_PreProcessing (-vpp):

Preprocess the Verilog files before translation them so that the Verilog compile directives can be elaborated and therefore supported

-Architecture_Name (-an):

Set the name of the generated VHDL architecture. The default name is "VeriArch"

-No_header [-nh]

Do not print SynaptiCAD header in the output file

-No_Verilog_PreProcessing [-novpp]

Disable the Verilog preprocessor (disables compiler directives) By default, the preprocessor is enabled.