Verilog Supported and Unsupported Constructs

The following constructs are supported by Verilog2VHDL.

Data Types

Supported

•wire, tri, supply0, supply1, memory, integer, time, real, reg, parameter

Not Supported

•net type(s) tri1, wand, triand, tri0, wor, trior, trireg

•expand range, charge strength, drive strength, delay specification for net declaration

Expressions

Supported

•operand types : net, register, bit-select, bit-slice

obinary logical operators:

oII, &&, !=, ==

obinary relational operators:

o<, <=, >, >=

•operand types : number, time, integer, net part-select, register part-select

ooperators:

o{}, arith. operators, mod, !, ===, !==, <<, >>, ?:

ounary operators:

o&, ~&, I, ~I, ^, ~^ or ^~

Continuous Assignment Statements

Supported

•Left hand side : net (vector or scalar), constant bit select of a vector net, constant part select of a vector net, concatenation

•Delays of type (rising) only, can be of (min/typ/max) type

•Net declaration Assignment

Not Supported

•drive strength

•delays of type (rising, falling, turnoff)

•(force, release continuous assignment

Procedural Assignments

Supported

•Left hand side : register (vector or scalar), constant bit select of a vector register, constant part select of a vector register, memory element, concatenation

•Blocking procedural assignment

•Non-blocking procedural assignment

•Delays of type min/typ/max

Not Supported

•procedural continuous assignment (assign, deassign, force, release)

Gate and Switch Level

Supported

•gate type: and, nand, nor, or, xor, xnor, buf, not, bufif0, bufif1, notif0, notif1

•Delays of type (rising) only, can be of (min/typ/max) type

Not Supported

•gate type: nmos, pmos, cmos, rnmos, rpmos, rcmos, tran, tranif0, tranif1, rtran, rtranif0, pullup, pulldown

•drive strength

•delays of type (rising, falling, turnoff)

Behavioral Modeling

Supported

•always

•initial

•conditional if-else-if

•case, casex, casez

•for

•forever, repeat, while loops

•tasks

•function calls

Not Supported

•named events

•parallel blocks (fork/join)

Hierarchical Structures

Supported

•module

•ports: input, output, inout

•module instantiation

•named port connection with concatenated names

•macromodule

Not Supported

•hierarchical names

System Tasks and Functions

Supported

•$display

•$fdisplay

•$write

•$fwrite

•$strobe

•$fstrobe

 Supported

•%b, %d format specification (%h and %o are treated as %b)

•scalars, vectors of nets and registers, string, time, integer type

 Not Supported

•Type conversions for scalars, vectors of nets and registers, string, time, integer type

•Format specification %c

•$readmemh

•$readmemb

 Supported

•1 entry per line in data file; only !//! type of comments

•No address or two addresses in $readmem call

•constant integer addresses

 Not Supported

•Multiple entries per line in memory data file; !/* */! type of comments

•One address in $readmem call

•vector addresses

•$fopen

•$fclose

•$time

•$realtime

•$timescale

•$rtoi

Not Supported

•all other system tasks

•all other system functions

Compiler Directives

Supported

•`timescale

•`define

•`ifdef / `ifndef (with vpp)

Not Supported

•all others

 

 

Recommended Verilog Coding Style

This section is devoted to making the user conversant with what is best translated by Verilog2VHDL. This is a very useful section for users who intend to use the tool on a continuous basis e.g library model developers. By enforcing the use of the constructs supported by verilog2vhdl in model development, a fully automatic VHDL translation can be achieved.

Verilog2VHDL supports a very large subset of the Verilog language. The user should read the Supported and unsupported section  for a complete understanding of supported constructs.

As a rule of the thumb, almost all synthesizable constructs are supported by the tool.

Unsupported constructs

The following constructs are NOT supported by Verilog2VHDL. The user is strongly advised not to use these constructs in the input file. The user is warned via messages when these constructs are encountered in the input description. Comments are also inserted in the output file to pinpoint the relative location of the unsupported construct.

All Verilog2VHDL generated comments have the following format:

- *** NOTE: In file <input filename>, at line <line number in input file>:

- *** NOTE: <message indicating the type of construct not translated>

If the user has indeed no choice but to use the following constructs, the Known problems section has information on the manual editing required to obtain equivalent VHDL.

Verilog constructs not supported are listed below:

•UDPs

•assign and deassign procedural assignments

•force and release procedural assignments

•parallel blocks

•task disable

•specify blocks

 

Supported Constructs

The following Verilog constructs are supported. When applicable, each sub-section also has some relevant do's, don'ts and caveats.

•Numbers:

All forms of numbers are supported. When using numbers in the binary, decimal, hex, or octal format always use sized vectors e.g 4'b 0010 for best results.

•Identifiers:

All VHDL keywords (see Verilog2VHDL User's and Reference Manual) are included in the Verilog2VHDL reserved list of identifiers.

oAvoid hierarchical names

oAvoid using identifiers differing only in case; VHDL is a case-insensitive language

oAvoid using extended identifiers if not generating VHDL-93

oMake sure the Verilog identifier conforms to the following VHDL identifier requirement: letter {_}letter_or_digit

•Data Types: Do not use

ostrengths in net declaration

onet types other than `wire', `tri0', `tri1', `supply0' and `supply1'.

•Operators and Expressions: Do not use

o`signed and `unsigned compiler directives

odelay of the type (mintypmax_expression, mintypmax_expression, mintypmax_expression).

•Continuous Assignments: Do not use

ostrengths in net assignment.

odelay of the type (mintypmax_expression, mintypmax_expression, mintypmax_expression).

•Procedural Assignments: Do not

odrive a Verilog register in more than one block. This can result in mismatches between synthesis and simulation models. If there are multiple drivers for a design, Verilog2VHDL inserts the code needed to turn off drivers of inactive processes.

ouse a non-blocking assignment with intra-assignment delay.

•Gate level Modeling:

•Do not use switches e.g nmos, pmos. All gates are supported.

•Module instantiation:

oDo not connect output ports using expressions; i.e do not use the concatenation operator in the expression.

ouse parameter value assignment.

•always and initial blocks:

•If a signal needs to be initialized in the initial block, it needs to be assigned before any VHDL wait statement. In such cases, the initialize is moved up as a signal (or variable) initialization statement.

•Tasks, Functions, Task enables and Function calls: Always

oDeclare tasks before they are called.

oDeclare functions before using them in function calls.

oIn functions, be sure to assign to the function return value or variables declared inside the function; i.e do not write to registers declared at the module level.

•System tasks and functions: Always

olimit the usage of system tasks and functions to those supported by the tool ( see supported System Tasks and Functions).

oavoid using $monitor{on,off} system tasks.