Timing Diagram Editing and Analysis

C.4 Compiling syncad_vhdl_lib  library with ModelSim

C.4 Compiling syncad_vhdl_lib  library with ModelSim

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C.4 Compiling syncad_vhdl_lib  library with ModelSim

 Previous topic This is the last topic  

The testbenches created by WaveFormer Lite use pre-written packages that must be compiled by ModelSim into a VHDL library called syncad_vhdl_lib. Below are the steps for creating this library and mapping the path to this library for ModelSim.

Compiling the syncad library with ModelSim (once per update of ModelSim):

Whenever you update your version of ModelSim, you will need to recompile the SynaptiCAD testbench library with the new ModelSim compiler by following the steps below:

•Start WaveFormer and select the Options > Simulator/Compiler Settings menu option to open the Simulator and Compiler Settings dialog.

modelsim_path

•From the Tool drop-down box, select the your particular ModelSim VHDL compiler. If you are not sure which version of ModelSim that you have, select ModelSim VHDL Command-Line XE/PE.

•Set the path where your ModelSim is located. For example, if you are using a version of ModelSim from Actel Libero on Windows, the Simulator Path will look something like:

          C:\Actel\Libero_8.6\Model\win32oem

•Press the Compile Syncad Libraries button to compile the SynaptiCAD Libraries. The first time that you set up a particular simulator or compiler you should press this button.

•You can view the results of this simulation by looking in the simulation.log tab of the Report window. If you cannot see the Report window, then choose the Window > Report menu option to bring the window to the front.

Map SynaptiCAD library to ModelSim:

Whenever you create a new project, you will need to inform ModelSim of the location of the syncad_vhdl_lib by running ModelSim's vmap command:

•Launch a DOS command prompt and change directory to your project's current working directory using the DOS cd command. Then run vmap using the options given below:

cd \synapticad\project\add4

vmap syncad_vhdl_lib "%APPDATA%\Synapticad\lib\vhdl\modelsim_vhdl_lib"