Agilent Equipment

WaveFormer File Type

16900 Series Timing Analysis System

Export with:

  Agilent 169xx Pattern Generator Full Mode

  Agilent 169xx Pattern Generator Half Mode

Import into WaveFormer using:

  Agilent Logic Analyzer (CSV)

16822A pattern generator

Export with:

  Agilent 169xx Pattern Generator Full Mode

  Agilent 169xx Pattern Generator Half Mode

Import into WaveFormer using:

  Agilent Logic Analyzer (CSV)

16700 Series Timing Analysis System with 16720 A pattern generator

Agilent 167xx Pattern Generator (binary) (PGB)

HP 16522A pattern generator card runinnd on the 16500 or 16600 Series Timing Analysis Systems

Agilent Pattern Generator(disk)

Agilent Pattern Generator (bus)

•Set the clocking signal: Make sure the timing diagram contains one clock signal, which will be used as the sampling clock. At each rising edge of the clock, the states of each signal will be written out to the clocks will be ignored. For more information see 11.3 Export General Instructions and the subsection on clocking signals.

•Must have at least one documentation marker. The first documentation marker found in the timing diagram generates the *M code line, which denotes the beginning of the main sequence (separating the initialization section from the main). If no documentation marker is present, the *M code is generated automatically and placed at the beginning of the data (just after VECT). Thus, only main sequences will appear (i.e., no initial sequences).

•Map the signals to the pattern generator pins using the pod mapping dialog described in section 11.4 Map Signals to Test Equipment Pins.

•Drawing the waveforms: Single-bit signal states should be drawn with only high and low segments. Virtual buses can contain Valid segments with virtual values that convert to high and low segments. Invalid, Tristate, and empty Valid segments are not supported by the HP16522A and generate an error message during export. The state of each signal is converted into a hexadecimal number and written to the file.

•Setup Tri-state enable signals: You can include tri-state enable signals in the exported data. To do this, select the signals that you want to create tri-state enable signals for and select the Import/Export > Add Tri-State Enables for Selected Signals menu option. This function will scan through the data signals and find each segment that is tri-stated or un-driven (blue) and create a high segment on the tri-state enable signals to match those segments. See 11.4 Map Signals to Test Equipment Pins.

•The end of the timing diagram is determined by the last edge of the longest drawn signal or an End Diagram Marker (note you must still have at least one documentation marker in addition to any End Diagram Marker that you add). If a signal ends early, its last state value is used until the end of the timing diagram.

•The HP16522A pattern generator has a limit of 126 signals per stimulus file, and a Group Bus limit of 32 signals per bus.

•The Bus and Disk versions generate basically the same code. The only difference is that the VECT code for the Bus version contains additional information.

•The *.hpd format is used for file transfer via network or diskette.

•The *.hpb format uses the HPIB bus for file transfer.