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(TD) 4.10 Exporting to SPICE, VHDL, and Verilog

(TD) 4.10 Exporting to SPICE, VHDL, and Verilog

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(TD) 4.10 Exporting to SPICE, VHDL, and Verilog

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WaveFormer Pro can export waveforms to many different formats by using the Import & Export > Export Timing Diagram menu and saving to the appropriate format.

Exporting Analog Signals To SPICE:

When exporting an analog signal to SPICE, the straight edges box in a signal's Analog Properties dialog determines whether the signal is modeled as piecewise-linear or as step voltages. Step voltages are approximated by adding an additional point in the spice PWL statement immediately after each drawn point. Digital signals always export to SPICE as quasi step voltages using PWL statements. To export to SPICE:

Choose the Import/Export > Export Timing Diagram As menu to open the Export As dialog.


Choose one of the Spice formats, like Spice sources from the Save as type box, then save the file. WaveFormer will save the file and also display it in the Report Window.


Notice the differences between the code for the RealRadix_Analog_Slanted and Real Radix_Analog_Straight signals that were drawn in the first section. When the straight edges box is checked, there are extra points where the voltage changes abruptly in a short period of time to represent the step voltage changes.


Exporting to VHDL or Verilog Simulators:

When exporting analog signals to a discrete event simulator such as VHDL or Verilog, analog signals must be exported as step voltages (discrete event simulators cannot model a true ramp, for example, so ramps must be approximated by step voltages). So regardless of whether an analog signal is being rendered piecewise-linear or as step voltages in the timing diagram window, it will export as step voltages to HDL simulators.

The export is performed as show above, except that one of the VHDL or Verilog formats is chosen in the Save As Type box,