SynaptiCAD Tutorials

(TD) 6.9 Incorporating Pre-written HDL Models into Waveformer Simuations

(TD) 6.9 Incorporating Pre-written HDL Models into Waveformer Simuations

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(TD) 6.9 Incorporating Pre-written HDL Models into Waveformer Simuations

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We will use an SRAM HDL module contained in an external file (sram.v) to model the SRAM. This model is fairly complex and accurately models the asynchronous interface that is commonly used by most off-the-shelf SRAMs. One special feature is that the SRAM resets all its memory cells to zero when it first starts up. In a real circuit, we would need to add extra logic to iterate through the addresses, writing zeros at each one. A full description of the Verilog modeling of this SRAM is outside the scope of this tutorial, but let’s take a quick look at it inside the Report window:

1. Select the Report > Open Report Tab menu option and open the file sram.v (located in the SynaptiCAD\lib\Verilog directory). Verify that you can view the file in the Report window. Keep this file open because we will be referring back to this file later in the tutorial.

9.1 Including an external SRAM Verilog model file into WaveFormer

To add the SRAM model to our design we need to modify the wavelib_exact.v file that contains the models used by WaveFormer. The SRAM model code cannot be entered into a signal’s HDL code window because the model declares a module and modules cannot be nested in Verilog (WaveFormer puts all the HDL code from signals into a single module called testbed). All user-written Verilog modules should be declared in wavelib_exact.v (or preferably, included from separate files into wavelib_exact.v using the include directive as will be doing). In this case, the source code for the SRAM is already contained in a separate file called sram.v and we only need to add an include statement to wavelib_exact.v to let WaveFormer know about it. To modify the wavelib_exact.v file:

1. Select the menu option Report > Open Report Tab and open the wavelib_exact.v file in the SynaptiCAD\hdl directory.

2. Add the following line to the beginning of the wavelib_exact.v (it may already be there depending on which SynaptiCAD product you are using): `include "lib\verilog\sram.v"

3. Select the Report > Save Report Tab menu option to save your change.

9.2 Instantiating the SRAM component models

To drive the data bus DBUS, we need to instantiate two instances of the SRAM model:

1. Create a new signal called DBUS.

2. Set the Radix to hex, set the MSB to 15, check the Simulate radio button, and select the Verilog radio button.

3. Enter the following HDL code into DBUS’s HDL code window:

wire CSB = !ENABLE;

sram BinMem1(CSB,READ,ADDR,DBUS[7:0]);

sram BinMem2(CSB,READ,ADDR,DBUS[15:8]);

The first line creates an internal signal that is an inverted version of the ENABLE line (the SRAM is active low enabled). The next two lines instantiate two 4Kx8 SRAMs and connect up their inputs and outputs (the first SRAM contains the low byte of the count and the second contains the high byte).