At this point all the timing diagrams have been created and you have edited the Sequencer process. Next we will generate the test bench and simulate the entire design, but we should first check to see if the simulator is setup properly.
TestBencher can control external simulators and compilers or use its built-in Verilog simulator to compile and simulate the design. If you are using the built-in simulator, skip ahead to next section. Step 7: Setup External Simulators in the TestBencher Pro online manual has a complete list of instructions for working with remote simulators and for setting up a compiler for TestBuilder.
To configure a third-party simulator:
•Choose the Options > Simulator and Compiler Settings menu option. This will open the Simulator and Compiler Settings dialog.
•From the Simulator and Compiler tools drop-down select the appropriate simulator.
•Enter the directory that contains the simulator executable in the Simulator Path edit box.
•Press Compile Syncad Libraries to build libraries required by the simulator in order to compile TestBencher projects. IMPORTANT: If you omit this step, you will get compile errors when you attempt to compile your test bench source files. This has to be done ONCE for each new simulator.
•Click OK to close the Simulator and Compiler Settings dialog.
Select the third-party simulator:
•Select the Project > Project Simulation Properties menu option. This will open the Project Simulation Properties dialog.
•Select the tab for the language you are working with.
•Select the desired simulator from the Simulator Type drop-down. If you are working in VHDL and using ModelSim XE/PE (but not SE), you should probably set this value to ModelSIM VHDL GUI, because XE and PE do not support the API required for TestBencher to capture the waveforms directly inside the GUI (the API is supported by ModelSim SE).
•Click OK to close the Project Simulation Properties dialog.