The VeriLogger simulator supports the following Verilog run time simulation options:

+maxdelays | +mindelays |+typdelays determines which delay used in the min:typ:max expressions. In the graphical simulator this command is set using the Project > Project Simulation Properties menu option. In the command line simulator add the option to the command line:

    vlogcmd cpu.v memory.v io.v +mindelays

+define+<macro name>+<macros name> ... defines macro names from the command line, generally for use with conditional compilation directives. Any number of macros can be defined by adding another +<macro name> to the list. For example, the count.v Verilog source code file had the following code fragment:

    'ifdef EXTEND

         $display("Using extended mode");

    'else

         $display("Using normal mode");

Then the following command will execute the first display statement:

      vlogcmd count.v +define+EXTEND

+synopsys (vlogcmd only) displays warnings for constructs that are either not supported or ignored by the Synopsys HDL Compiler.

+noshow_var_change (vlogcmd only) disables the tracking of variable changes. By default, VeriLogger keeps track of the location and simulation time where variables are last written. This information can be displayed using the $showvars directive. This feature may cause slight performance degradation, so it can be disabled with this option.

+libext+<ext>+<ext> ... specifies the filename extension used when searching for libraries in the library directory. This is most often used with the -y option. The following example will search the directory \design\libs for libraries whose filename ends with .vl and .vv:

    vlogcmd cpu.v -y \design\libs +libext+.vl+.vv

+incdir+<directory1>+<directory2>+... specifies the directories that VeriLogger will search for included files. All the characters between the pluses are used in the directory name.

    vlogcmd cpu.v +incdir+\design\project1+ -y \design\libs +libext+.vl+.vv

+loadpli1=<pli_library_name.dll>:<register_function1>, <register_function2>, … Specifies the PLI library name that contains a list of PLI tasks and functions to execute. VeriLogger is expecting the library to contain a s_tcell array called veriusertfs that contains a list of PLI user tasks and functions. You can also group related PLI commands into register functions so that you can partially load commands from the PLI library. The register function should contain a veriusertfs array and return a pointer to that veriusertfs array.  Here are some examples of using the option:

vlogcmd +loadpli1=myplilib.dll

vlogcmd +loadpli1=myplilib.dll:register_my_tasks

vlogcmd +loadpli1=myplilib.dll:register_my_tasks1,register_my_tasks2

Here is a code example of a register function containing the veriusertfs array:

    s_tfcell* register_syncad_tasks()

     {

     static s_tfcell veriusertfs[30] =

       {

       /*** Template for an entry:

       { usertask|userfunction, data, checktf(), sizetf(), calltf(), 

         misctf(), "$tfname", forwref?, Vtool?, ErrMsg? },

        Example:

        { usertask, 0, my_check, 0, my_func, my_misctf, "$my_task" },

         ***/

        /*** final entry must be 0 ***/

         {0}

        }

     return veriusertfs;

     }