6.3 SmartModels (Swift Models)

SmartModels (also known as Swift models) are behavioral simulation models distributed as binary object files to hide their internal representation from end users. The SWIFT standard was created by Synopsys as a way of creating and distributing binary models so that they can be simulated by any simulator licensed to support the SWIFT standard. Theoretically, Synopsys has declared the Swift standard obsolete, but many FPGA vendors currently distribute Swift-based simulation models for their IP.

To use a SmartModel, you first need to create a Verilog or VHDL wrapper module (currently only Verilog wrapper modules are supported) for the model using smartmodel_wrapper_generator.exe and then you can instantiate instances of this module in your design. For most users, its generally best to create wrappers for all of your SmartModels at one time.The section below discusses the process of creating wrapper modules in more detail.

Generating SmartModel Wrappers and Using SmartModels with VeriLogger Extreme

•To incorporate a SmartModel into a simulation, first set the environment variable LMC_HOME to point to the directory containing your SmartModels.

set LMC_HOME=c:\tools\swift

•Then generate a Verilog wrapper module for each SmartModel using the smartmodel_wrapper_generator.exe the program located in SynaptiCAD/bin directory. The example below generates a Verilog file called DCC_FPGACORE.v that contains the Verilog wrapper module for the SmartModel called dcc_fpgacore.

smartmodel_wrapper_generator -verilog -u dcc_fpgacore

•You can optionally hand-edit this module to reorder ports, select different defaults for the parameters of the module, etc.

•smartmodel_wrapper_generator usage:

smartmodel_wrapper_generator -verilog|-vhdl [-bit2bus] [-u] [<sm_name>]

-verilog - Verilog generation;

-vhdl - VHDL generation;

-bit2bus - generate additional parent wrapper with buses;

-u - use uppercase letters for naming modules;

<sm_name> - name of SmartModel to generate (by default wrappers for all found SmartModels will be generated into appropriate output files)

•Next, declare instances of these wrapper modules in your design using normal Verilog module instantiation rules, and parameterize the instance as desired.

•Compile the wrapper files along with the rest of your design files using VeriLogger Extreme. These wrapper files can only be used with VeriLogger Extreme.

•If you are using BugHunter, just add the wrapper files to the User Source Files folder in the Project window (see Step 4: Add Source files to the Project).

•If you are using the command line version of VeriLogger Extreme just add the wrapper files to the simx command line. Unlike VCS, VeriLogger Extreme can detect a SmartModel wrapper file and does not need the -lmc_swift directive.