If you are using the command line version of the translator, you can control the translator by adding command line arguments after listing the file(s) to be translated:

vhdl2verilog input_file [output_file] [options] [-Help] 

                        [-Usage] [-Version] 

where option can be one or all of

[-File {file_name}] [-Replace] [-Silent] [-No_Comments] [-Debug]

[-No_Default_defines] [-No_Package_translation {package_file_names}]

[No_Component_Check] [-Include_Package_files] [-Function_Map {files}]

[-Ignore_Subprogram_Calls] [-Translate_Subprogram_Bodies]

[Preserve_Generate] [Support_Multi-dimensional array] [Ignore_Integer_Range]

[Support_Directives] [-Force_Lower_Case] [-Time_Scale {time}]

[-Log {logfile_name}] [-SYNTHesis] [-87] [-No_header] [-No_timescale]

Translation Option Summary

-File {file_name} [-f {file_name}]:

Read command line arguments from the specified file

-Replace [-r]:

Replace the existing output_file with the new output_file ; default is to backup the output_file to <output_file_name>.old

-Silent [-s]:

Suppress printing out of messages indicating translator actions

-No_Comments [-nc]:

Supress extraction of comments from input HDL file

-Debug [-d]:

Prints debug messages from the tool

-No_Default_defines [-nd]:

Verilog define directives for TRUE and FALSE are present in all output files; use of this switch suppresses printing of default defines

-No_Package_translation {package_names} [-np {package_names}]:

Packages with <package_name> or having <package_name> as prefix are not translated; this can be used to suppress translation of specific packages.

-No_Component_Check [-ncc]:

Translation will proceed even if some component definitions or entity declarations are missing; this can be used to force translation of individual components without all its components; the translation result might not compile because of the absence of its component. This option is especially useful when translating files that reference encrypted IP components for which definitions are not available.

-Include_Package_files [-ip]:

Use of this switch will direct the translator to write the translation of packages into files '<package_name>_package.verilog' and '<package_name>_modules.verilog'; default is to include them in the output file

-Function_Map {files} [-fm {files}]:

Load one or more function map files that describe how to map functions and procedures to their Verilog counterparts. For details on creating and using function map files, see Chapter 9.4 Mapping Functions and Procedures.

-Ignore_Subprogram_Calls [-isc]:

Do not translate the headers of function and procedure calls.

-Translate_Subprogram_Bodies [-tsb]:

Translate the bodies of functions and procedures into a separate file (overrides the -isc switch). By default, subprogram bodies will not be translated. Translation is done on unconditional basis: output is not guaranteed to work.

-Preserve_Generate [-pg]:

Preserve generate statement. Generate Statements will not be elaborated if the concurrent body contains only concurrent assignments

-Support_Multi-dimensional_array [-sm]:

Bit-wise access of multi-dimensional array will be translated. Additional signals or subprograms may be created for translating multi-dimensional arrays

-Ignore_Integer_Range [-iir]:

Ignore the integer range and translate VHDL integers to 32 bit Verilog integers

-Support_Directives [-sdi]:

Support translation directives. This disables and enables translation of code between the following directives: translate_off/translate_on, synopsys translate_on/synopsys_translate_off,pragma_translate_on/pragma translate_off,  synthesis_translate_on/synthesis translate_off, and ambit_translate_on/ambit translate_off.

-Force_Lower_Case [-flc]:

Changes all identifiers to lower case

-Time_Scale {timescale} [-ts {timescale}]:

Set the Verilog 'timescale

-Log {logfile_name} [-l {logfile_name}]:

Logs translator messages into file <logfile_name>; default log file is 'vhdl2v.log'

-SYNTHesis [-synth]:

Produces synthesizable code; presently restricted to suppressing initial statements and using '==' Verilog operators instead of '===' operators

-87 [-87]:

Disable support for VHDL-93; enable VHDL-87 support instead.

-No_header [-nh]

Do not print SynaptiCAD header in the output file.

-No_timescale [-nt]

Do not print timescale directive in the output file. Default is OFF(timescale is printed in the output file).

-Save_Parenthesis [-sp]

Inserts parenthesis in expressions to prevent confusions about precedence of operators.

-Blocking [-bl]

Use blocking assignments in all combinational procedural blocks

-Force_If_Generate [-fig]

Force translation of 'if_generate' statement even when the 'if' condition evaluates to false. The result may not be equivalent to the input when this option is set.  Manual editing of the translation result may be necessary."