BugHunter Pro and the VeriLogger Simulators
- $ -
$display
$dumpall
$dumpfile
$dumpoff
$dumpon
$dumpvars
$monitor
- _ -
__syncad
- ` -
`pragma protect directives
- + -
+access
+afile
+append_log
+define+macroname
+define+macroname[=macrovalue]
+defparam+parameter_path=value
+diagnostic
+epulse_neg
+epulse_noneg
+epulse_ondetect
+epulse_onevent
+error
+failure
+linedebug
+loadpli1
+loadpli1=<arg>
+loadvpi
+loadvpi=<arg>
+maxdelays
+mindelays
+mti_compat
+no_notifier
+nocopyright
+nospecify
+nostdout
+notchkmsg
+note
+notimingcheck
+pathpulse
+protect
+pulse_e
+pulse_int_e
+pulse_int_r
+pulse_path_e
+pulse_path_r
+pulse_r
+scd_dbgsymbols
+scd_msg_enable+msg_level
+tcl+<file>
+tcl+filename
+transport_path_delays
+typdelays
+version
+warning
- A -
Add
files to project
AES
Auto Parse Project on Load
Auto-Grab Top Level Signals
- B -
Back-annotated Simulation
base64
Batch file
Bit-Slicing Simulated Waveforms
Blowfish
Break at Time Zero
breakpoints
btim_AddDumpSignal
btim_closedumpfile
btim_dumpfile
Build Button
Building a project
- C -
C++
Cadence batch file
Capture and Show Waveforms of Watched Signals
CAST
Clear Log File Before Compile
Color Highlighting
command line simulator
Commonly used options
Debug and Logging Options
Miscellaneous Options
options
Override Parameter Values
PLI & VPI Options
preparing Verilog source files for
SDF Timing Options
Simulation Build Options
simulation control commands
Specify block Options
Compile Library
Compile Source Files of Type
Compiler
Compiling
Component Libraries
Configurations for simulation
console window
controlling simulation from
Controlling Simulation
--create (-c)
- D -
db_addtimebreak
db_disabletimebreak
db_enabletimebreak
db_finish
db_getbasictype
db_getcurrenttime
db_getvalue
db_printinteractivescope
db_printinternaltimeprecision
db_removetimebreak
db_setinteractivescope
debug
--delete (-d)
DES
Destination Library
Diagram Configuration
Disable Periodic Waveform Update
Drivers
--dump [library_name]
- E -
Editor Window
creating files
external editors
File Location Buttons
Find in Files
Find in multiple files
Find Signal Declaration from Diagram
font
Goto Current Executed Statement
Introduction
Jump to Line number
Key Commands
line numbers
opening files
Project Navigation
saving files
Search Active Editor Box
Syntax Highlighting with Color
tab width
XEmacs
Editor/Report Preferences dialog
Color Printing checkbox
Editor Background Color button
Editor/Report Font button
Insert Spaces button
Keep Tabs button
Show Line Numbers checkbox
XEmacs integration
Encrypted Models
- F -
-f
-f <filename>
Faster Simulation
Faster Simulation Times
Filter Constants and Parameters
Filter Empty Processes
Find Breakpoints
Find Errors
Find in Project menu usage
Find with Search Box
Font for Editor
FPGA Libraries
- G -
gcc C++ compiler
Generate Test Bench on Build Project
Goto to line number
-gparameter_path=value
- H -
-h
--help (-h)
- I -
init_syncad
Inspect Values dialog
- L -
-l <filename>
Libraries
Line numbers
--list (-l)
Log File name
- M -
Make Arrays Watchable
Make Constants and Parameters Watchable
--map (-m)
-map_file
Mentor batch file
ModelSim batch file
- N -
NCSim batch file
- O -
-o filename
On-Event and On-Detect Pulse Filtering
Override Subproject Properties during Simulation
- P -
Pause button
PLI 1
PLI 2.0
pragma protect directives
predefined macros
Private Keys
Project Configurations
Project Simulation Properties dialog
Detailed Overview
Getting Started
Project Window
Editor Links
projects
adding files
building
VeriLogger
Protected Envelopes
Public Keys
- R -
-R
--scd_msg_enable <msg_level>=0|1
-r <snapshot>
race condition detection
RSA
Run Button
- S -
-s
--scd_cleanup_objs
--scd_immediate_sensitivity
--scd_invert_queue
--scd_jobs=n
--scd_mtilike_queue
--scd_ncsimliketchkmsg
--scd_no_prefix
--scd_nosim
--scd_randomize_queue
--scd_source_info_at_declaration
--scd_source_info_at_reference
--scd_top [unitname]
--scd_usemake
Scope
Copy To Buffer
Setting
SDF (Standard Delay File)
Set Destination Library for Compiled File menu
Show All Drivers menu
Show Drivers window
signals
Watch
Simulate
Simulation
back-annotated
command-line simulator
faster trick
speeding up
Simulation Running
Simulation Started
Simulator
32 bit operation
64 bit operation
path
Simulator / Compiler Settings dialog
Simulator Settings button
Simx
simx32
simx64
Simxlib
simxloader
Simxsim
Snapshot
overview
Standard Delay File (SDF)
Status Bar
Step 1 - Configuring BugHunter for your Simulator
Step 2 - Setup the Project Simulation Properties
Step 3 - Create a Project
Step 4 Add Source Files to the Project
Step 5 Draw a Test Bench
Step 6 Build the Project and Set the top-level module
Step 7 Simulate and Debug
Step 8 Save the Project
Stimulus & Results diagram
Stop button
Synopsys batch file
Syntax Highlighting in Editor
SystemC
Linux
Windows
- T -
Tab Width for Editor
Template Configurations
Top-level module
Translation
Setup for translation
Verilog to VHDL
VHDL to Verilog
- U -
--unmap (-u)
uuencode
- V -
-v <LibraryFilename>
VCS batch file
Verilog 2005
compilation
technology
VeriLogger Extreme Command Line tools Simx and Simxsim
Visual Studio C++ compiler
Vlogcmd
+define
+incdir
+libext
+noshow_var_change
+synopsys (vlogcmd only)
specific commands
Vlogcmd (old VeriLogger Pro) interpreted simulator
VPI
- W -
Watch signals
Watched Signal Bit Slice
--work <worklib>
- X -
- Y -
-y <LibraryDirectory>
