• BugHunter Pro and VeriLogger Introduction
• Chapter 1: Getting Started with BugHunter
  • Step 1: Configuring BugHunter for your Simulator(s)
  • Step 2: Setup the Project Simulation Options
  • Step 3: Create a Project
  • Step 4: Add Source Files to the Project
  • Step 5: Draw a Test Bench (optional)
  • Step 6: Build the Project and Set the top
  • Step 7: Simulate and Debug - General Overview
  • Step 8: Save the Project, Code and Waveform Files
• Chapter 2: Simulation and Debugging Functions
  • 2.1 Project Simulation Properties
  • 2.2 Build and Simulate
  • 2.3 Watching Signal and Component Waveforms
  • 2.4 Breakpoints
  • 2.5 Inspect And Edit Values
  • 2.6 Find Drivers
  • 2.7 Report Window Error and Log file tabs
  • 2.8 Command Console for Interactive Debugging
  • 2.9 Source Code Libraries
  • 2.10 Compiled Libraries (Symbolic Libaries)
  • 2.11 Using VPI applications to interface to the simulator
  • 2.12 Compiling Command-Line Based Designs with BugHunter
  • 2.13 Project Window Overview
• Chapter 3: Waveforms and Test Bench Generation
  • 3.1 Stimulus and Results Diagram
  • 3.2 Drawing Waveforms for Stimulus Generation
  • 3.3 Zooming, Scrolling, Measuring, and Searching
  • 3.4 Bit-Slicing a Watched Signal
  • 3.5 Waveform Comparisons (Optional Features)
  • 3.6 Generating and Reading VCD and BTIM Files
• Chapter 4: Editor Functions and Code Navigation
  • 4.1 Opening, Saving, and Creating New Source Code
  • 4.2 Navigating Code with Buttons and Report Tabs
  • 4.3 Navigating Code with the Project Window
  • 4.4 Fast HDL Code Editing
  • 4.5 Searching in the Project Window
  • 4.6 Editor and Report Window Commands
  • 4.7 The Editor/Report Preferences Dialog
  • 4.8 XEmacs Integration and other External Editors
  • 4.9 Editor Window Overview
• Chapter 5: VeriLogger Command Line Tools
  • 5.1 VeriLogger Extreme tools: Simx and Simxloader
  • 5.2 Preparing Verilog Source files
  • 5.3 Batch Files for Command Line Simulators
  • 5.4 Simx Commonly used Command Line Options
  • 5.5 Simx: Compiler/Elaborator
  • 5.6 Debug and Logging Options
  • 5.7 Specify Block and SDF Timing Options
  • 5.8 Overriding Parameter Value Options
  • 5.9 Loading a PLI application
  • 5.10 Simx Miscellaneous Options
  • 5.11 Simxloader: Simulator
  • 5.12 Simxloader Race Detection Options
  • 5.13 Simxlib: Compiled Library Utility
  • 5.14 VeriLogger Pro tools: Vlogcmd
  • 5.15 Vlogcmd Simulator Control Commands
  • 5.16 Vlogcmd Predefined Plus Options
• Chapter 6: SDF, Encrypted Models, and SmartModels
  • 6.1 Using a Standard Delay File (SDF)
  • 6.2 Verilog Protected Envelopes (Encrypted Models)
  • 6.3 SmartModels (Swift Models)
• Chapter 7: Speed Tricks and Techniques
  • 7.1 Dumping Simulation Waveforms
  • 7.2 What not to Watch
  • 7.3 Eliminate 5 Second Waveform Updates
• Chapter 8: Verilog2VHDL Translation
  • 8.1 Graphical Interface for Translation
  • 8.2 Verilog2VHDL Translation Options
  • 8.3 Compiling and Simulating VHDL Output
  • 8.4 Frequently Asked Questions: Verilog2 VHDL
  • 8.5 Recommended Modeling Style Verilog
  • 8.6 Verilog2VHDL Known Issues
  • 8.7 Verilog2VHDL Release Notes
• Chapter 9: VHDL2Verilog Translation
  • 9.1 Graphical Interface for Translation
  • 9.2 VHDL2Verilog Translation Options
  • 9.3 Mapping VHDL packages to file locations
  • 9.4 Mapping Functions and Procedures
  • 9.5 Translating Functions and Procedures
  • 9.6 D-FlipFlop Mapping
  • 9.7 Importing (parts of) Verilog files
  • 9.8 Reserved Verilog Keywords
  • 9.9 Frequently Asked questions VHDL2Verilog
  • 9.10 Recommended Modeling Style VHDL
  • 9.11 VHDL2Verliog Known Issues
  • 9.12 VHDL2Verilog Release Notes
• Chapter10: C++ and SystemC
  • 10.1 Setting up Visual Studio C++ for Windows
  • 10.2 Setting up gcc for Linux Machines
  • 10.3 Building and Running SystemC simulations
  • 10.4 Learning SystemC
• Chapter 11: Schematic Viewing of Gate Level Designs
  • 11.1 Gates-On-The-Fly Install and License
  • 11.2 Launching the Schematic window
  • 11.3 General GOF Information
• Chapter 12: SimSwapper Simulator Command-Line Swapper
  • 12.1 SimSwapper Quick Start
  • 12.2 Passing Command Line Options to SimSwapper
  • 12.3 SimSwapper Translation Modes
  • 12.4 SimSwapper Configuration
  • 12.5 SimSwapper Command Line Options
• Appendix A: BugHunter System Tasks
  • init_syncad
  • btim_dumpfile
  • btim_closedumpfile
  • btim_AddDumpSignal
  • db_getcurrenttime
  • db_printinteractivescope
  • db_finish
  • db_addtimebreak
  • db_removetimebreak
  • db_enabletimebreak
  • db_disabletimebreak
  • db_getbasictype
  • db_getvalue
  • db_printinternaltimeprecision
  • db_setinteractivescope
  • Enabling BTIM dump commands in command-line simulator
• Appendix B: Verilog2VHDL Translation Reference
• Appendix C: VHDL2Verilog Translation Reference

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