• TestBencher Pro and Reactive Test Bench Manual
• Chapter 1A: TestBencher Pro Design Flow
  • Step 1: Create a New Project
  • Step 2: Add the MUT to the Project
  • Step 3: Extract Ports into Template Diagram
  • Step 4: Create the Timing Transactor Diagrams
  • Step 5: Define Sequencer Process
  • Step 6: Generate the Test Bench
  • Step 7: Setup External Simulators
  • Step 8: Simulate the Test Bench
  • Step 9: Learning more about TestBencher Pro
• Chapter 1B: Reactive Test Bench Option Design Flow
  • Step 1: Create a Project to hold the MUT
  • Step 2: Create the Reactive Diagram
  • Step 3: Generate the Reactive Test Bench
• Chapter 2: Timing Transactor Basics
  • 2.1 TestBencher Transactor Waveform Initilalization
  • 2.2 Drawing Waveforms
  • 2.3 Waveform Colors and Bi-Directional signals
  • 2.4 Waveform States with Variables and Conditions
  • 2.5 Simulated Signals
  • 2.6 Sensitive Edges - a Blocking Construct
  • 2.7 Controlling the Triggering Order of Parameters
  • 2.8 Adding Signals Manually
  • 2.9 Transactor Clock Domains and Waveform Code Generation
  • 2.10 Debugging Transactor Clock Domains
• Chapter 3: Transaction Samples
  • 3.1 Adding a Sample
  • 3.2 Sample Checking and Actions
  • 3.3 Samples that Block Clock Domains
  • 3.4 Samples Triggering a Delayed Transition or Another Sample
  • 3.5 Using Sample Variables
  • 3.6 Storing Sample Values in User Defined Variables
• Chapter 4: Transaction Delays, Setups, and Holds
  • 4.1 Delays
  • 4.2 Setups and Holds
  • 4.3 Creating Continuous Setups and Holds
• Chapter 5: Transaction Markers
  • 5.1 Adding a Marker to a Diagram
  • 5.2 End Diagram Markers
  • 5.3 Pause Simulation Marker (Verilog Only)
  • 5.4 Wait Until Marker
  • 5.5 Loop Markers
  • 5.6 HDL Code Markers
  • 5.7 Semaphore Markers (TestBencher Pro only)
  • 5.8 Pipeline Boundary Markers (TestBencher Pro only)
  • 5.9 Documentation and Time Break Markers
• Chapter 6: Classes, Variables, and Files
  • 6.1 Variables
  • 6.2 Classes
  • 6.3 Class Methods
  • 6.4 Class Libraries
  • 6.5 Random Number Generation and Constraints
  • 6.6 Data Packing and Bit Streams
  • 6.7 SynaptiCAD Test Vector File Format
  • 6.8 Output Data to a File (VHDL & Verilog)
  • 6.9 Input Data Dynamically from a File (VHDL)
  • 6.10 (Verilog) Initialize Array from File
  • 6.11 (VHDL) Initialize Array from File
  • 6.12 Variables and Class Field Properties
  • 6.13 Language Independent Types
• Chapter 7: Transaction-Level Model and Transaction Sequencer
  • 7.1 Template, Sequencer, and Transaction Calls
  • 7.2 Master and Slave Transactions
  • 7.3 Transaction Manager Overview
  • 7.4 VHDL: TM fill with Post calls
  • 7.5 VHDL: TM fill from a File
  • 7.6 VHDL: TM fill from Random Generator
  • 7.7 Randomizing Transaction Inputs
  • 7.8 Changing a Project Template File
• Chapter 8: Simulating a Test Bench
  • 8.1 Simulate the Test Bench and Design
  • 8.2 Project Simulation Properties Dialog
  • 8.3 TestBencher Simulation Modes
  • 8.4 Generate Command Files for Third Party Simulators
  • 8.5 Parsing Package Files into Libraries
• Chapter 9: Advanced Project Features and Properties
  • 9.1 Sub-Projects
  • 9.2 Component Instances of Sub-Projects
  • 9.3 Golden Reference Models
  • 9.4 Libraries and Use Clauses dialog (VHDL)
  • 9.5 Signals and Ports for Components dialog
  • 9.6 Project Generation Properties dialog
  • 9.7 Diagram Properties dialog
  • 9.8 Diagram Settings dialog (TestBencher only)
  • 9.9 Project Menu and New Project Wizard dialog
• Chapter 10: Test Bench Techniques and Examples
  • 10.1 Pipeline Transactions
  • 10.2 Waiting for Signal Transitions or Conditions
  • 10.3 Burst Mode Transactions
  • 10.4 Conditionally Moving Signal Edges (Sweep Tests)
  • 10.5 Reading and Writing Serial Data
  • 10.6 Testing a Counter Model
  • 10.7 Different ways to bring in External Models
  • 10.8 Different ways to Loop
  • 10.9 Scoreboarding
• Chapter 11: Language Specific Details and Test Bench Architecture
  • 11.1 Verilog
  • 11.2 VHDL
  • 11.3 TestBuilder
• Appendix A: Editor Commands
• Appendix B: Supported Simulators
• Appendix C: Language Independent Operators

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