- 2 -

2_state

2_state_vector

- 4 -

4_state

4_state_vector

- A -

Abort Transaction

Absolute Markers

Absolute Samples

add to diagram

definition

Advanced Register and Latch Controls dialog

Apply Call

no-wait

wait

Apply Statements

adding to template file

in TestBuilder

in Verilog

in VHDL

ApplyFile

ApplyFile_nowait

ApplyNextTransaction

array

Verilog Initialize from file

VHDL Initialize from file

Arrays

associative array

Associative Arrays

Attach to Edge

Attach to Time

Auto Parse Project on Load

Auto Run

Auto-Adjust Display Label Position Markers

- B -

Bi-Directional Signals

Big Endian

Bit Order

Bit Slice

Bit Stream Packing

Blocking Construct

Example

Samples

Sensitive Edges

Wait Until Marker

bool

Boolean Conidtion For Delay

Boolean Equations

Break at Time Zero

BugHunter Project

converting to TestBencher

Burst Mode Transactions

Buses

adding to diagrams

byte

Byte Order

- C -

C++

C++ compiler

Capture and Show Watched Signals

Class Libraries

Overview

Class Library List

Class Methods

adding to a class

Class Level methods

Diagram Level methods

Project Level methods

Classes

defining fields for

Overview

Classes and Variables Dialog

constrained random generation

defining constraints for

defining fields for

Definition of Types and properties

View Variables

Clear Log File Before Compile

Clock Domain

Blocking Samples

Overview

Sensitive Edges

Waveform Code Generation

Clocks

adding to diagrams

Code Generarion

Enable Sample, Delay, Marker

Code Generation Options Dialog

Blocking Samples

Colors of Waveforms

Command File - Generating

Compile the Active Project

Component Instance Generation Properties menu

Component Model

Class Methods

default port mapping

definition of sub-project

instance of sub-project

port mappings

Sequencer Process

Concurrent Apply

Conditional State Transitions

Constrain Input Data

Constrained Random Number Generation

Constraints

defining for a class

Continuous Setups and Holds

Count Clock Edges

Create Component Instance

Critical Regions

defining

Cycle Based Properties

- D -

Data Packing

in Verilog

Debug Run

Default Clock

Default Delay After Clock Edge

As Drawn

Fixed

Define from Template button

Delayed State Transitions

Delays

code generation

conditional

creating

Delay Code Generation min, max, typical

Enable Code Generation for all

Overview

specifying the order of

triggered by samples

Verbose for all

Design Flow

Diagram Properties Dialog

cycle based properties

default clocking domain

including Library Files

Diagram Settings dialog

Code Generation

Default Delay After Clock Edge

default settings

Display Applied Inputs

during project creation

Enable Abort Code

Instance Setting

Master Transactor

Project Simulation Properties

Signal HDL Direction and Type

Slave Transactor

TimeOut

Verbose Samples, Delays, Markers, Sensitive Edges

Diagram Variables

in waveforms

Diagrams

creating

template diagram

view generated source code

Direction

Direction of classes or variables

Direction Waveform Segment

Display Applied Inputs

Display Signal States Markers

Documentation Markers

Drawing Waveforms

Driven Flags

Driving Events

Dump Watched Signals

- E -

Edge Properties Dialog

Trigger Order

Edit Bus State Dialog

conditional states

Driven flag

Variables

Editor

keyboard shortcuts

Editor Commands

element

Enable Abort Code

Enable Code Generation

Delays

Setups and Holds

Enable Delay HDL Code Generation

Enable HDL Code Generation

for Samples

Samples

Enable Marker HDL Code Generation

Enable Reference Model

how-to

Enable Sample HDL Code Generation

Enable TestBuilder Integration

Enable Variable

Sample

End Diagram Markers

End Loop Marker

End Transaction

event

Events

Examples

Overview

Exit Loop When

Export as BugHunter Project

External Program Integration

External Program Settings

External Simulators

Extract Ports from MUT

- F -

Falling Edge Sensitive

Field Name

Fields

defining from file

File data initialize Array (Verilog)

File data initialize Array (VHDL)

File Input

File Output

File Structure Types

fixed_len_string

For Loop Markers

Full Expect

functions

- G -

Generate Test Bench

Generate Test Bench on Build Project

Generated Code

controlling

Generating Constrained Random Data

in TestBuilder

Golden Reference Model

Grab Top Level Singals

- H -

HDL Code Button

HDL Code Generation button

Delays

Setups and Holds

HDL Code Markers

Holds

continuous

creating

Enable Code Generation for all

outward arrows

Overview

properties

specifying the order of

Verbose for all

- I -

If-Then-Else Sample Code

Include Directories

Including Library Files

Initial value

Initialization Diagram

Initialize Array from file (Verilog)

Initialize Array from file (VHDL)

Inout Signals

Insert Diagram Calls

Insert into Equation

Instance Count for Pipelines

Instance Setting

int

Is Apply Subroutine Input

for Samples

Is Apply Subroutine Input control

Delays

Setups and Holds

- K -

Keyboard Shortcuts in Editor Windows

- L -

Language

details specific per

Libraries (VHDL)

Library Directories

Library Extensions

Library Files

class libraries

including in diagrams

Little Endian

Loop Until Markers

Looping Markers

LSB

- M -

Make Parameters Watchable

Make TB button

Margin

Markers

absolute

attach to edge

attach to time

created

Documentation type

Enable Code Generation for all

End diagram type

HDL Code type

looping types

overview

Pause Simulation (Verilog) type

Pipeline type

relative

semaphore type

specifying the order of

Time Break type

Verbose

Wait Until Type

Master

Master Transactions

Master Transactor

Diagram Setting

Model Under Test (also see MUT)

ModelSim

MSB

Multiplier

MUT

adding to the project

extracting ports

- N -

NC Verilog

Network Packing

New Diagram Defaults

New Project Wizard dialog

- O -

Outward Arrows

- P -

Packing

in Verilog

in VHDL

Parameters

Delays

Holds

samples

Setups

specifying the order of

temporal expressions

Pause Simulation (Verilog) Markers

Pause Simulation (VHDL work around)

Pipeline

Instance Setting

Pipeline Boundary Markers

Point Samples

add to diagram

definition

Port Mappings

component instances

default for component definitions

Post Calls

VHDL

Post Semaphore Marker

PostRandomTransactionType

Project

adding files to

chaning template files

Chapter overview

Class Library List

Component Instance Generation Properties menu

Component Model

creating

Default Diagram Settings

directory

Enable TestBuilder Integration

Language

Project Generation Properties menu

Quick steps overview

saving

Project Generation Properties dialog

Add Timestamp to Each File

Enable Reference Model

Instance Name

Prefix Generated Files With

Source Indent Size

Transaction Recording

Verbose Transaction Logging

Project Generation Properties menu/dlg

Project Library

definitions of components

instances of components

Project Simulation Properties

Project Simulation Properties dialog

Auto Parse Project on Load

Break at Time Zero

Capture and Show Watched Signals

Clear Log File Before Compile

Dump Watched Signals

Generate Test Bench on Build Project

Grab Top Level Singals

Include Directories

Library Directories

Make Parameters Watchable

Project Variables

accessing in Verilog

- Q -

queue

queuePath

Queues

- R -

Rand

Randc

Random Data

Random Transactions

Randomization

in TestBuilder

Randomize function

Reactive Test Bench

Overview

Step 1: Create Project and Extract Ports

Step 2: Draw Test Bench

Step 3: Generate the Reactive Test Bench

real

Reference Model

Relative Markers

Relative Samples

add to diagram

definition

Repeat Loops Markers

Rising Edge Sensitive

Run Simulation

RunRandomTransaction

- S -

Sample

Enable Code Generation

Verbose

Sample Properties Dialog

Enable HDL Code Generation

HDL Code Button

Is Apply Subroutine Input

Samples

Actions

adding

Blocking

defined

Enable Variable

Full Expect

If Condition

Multiplier

point

relative

Sample Properties dialog

Sample Variable and Flag

self-testing code

specifying the order of

State Matches

Store Sampled Value as a Subroutine Output

Then/Else Action

triggering delayed state transitions

triggering other samples

scoreboarding

Select Packing Options dialog

Select Variable Dialog

Self-Testing Code

Samples

Semaphores

Markers

Sensitive Edges

Code Generation

Defining

Verbose

Sequence Recognition

ordering events

Sequencer Process

Overview

used to sequence transactions

Sequencing Transactions

Serial Data

SetApplyCallMode

SetTransactorWeightings

Setups

continuous

creating

Enable Code Generation for all

outward arrows

Overview

properties

specifying the order of

Verbose for all

Signal HDL - Direction and Type

Signal Properties dialog

Sensitive Edges

Signals

adding to diagrams

advanced register

clocked

direction

Direction Inout

drawing

driving events on

properties

Signals and Ports

of Component Model

Signals and Ports dialog

menus to open

Port Mappings

signed_logic

Simulated Signals

Simulation

project properties

test bench

with third party simulators

Simulation Button Bar

Simulation Files

needed for TestBuilder

needed for Verilog

Simulation Mode

Auto Run

Debug Run

Simulator and Compiler Settings dialog

Size

Slave

Slave Transactions

Slave Transactor

Diagram Setting

Source Code

for Class Methods

generated for diagrams

Spacer

adding to diagrams

State Matches - Samples

State Transitions

conditional

waiting for

State Variables

in waveforms

Static

std_logic

std_logic_vector

std_ulogic

std_ulogic_vector

Store Sampled Value as a Subroutine Output

Structure Type

Sub-Project

Design Flow

instances of components

Supported Simulators

Sweep Test

- T -

tasks

tb_control VHDL variable

tb_LocalBfmPath VHDL variable

tbench

tbsyslog

Template Diagram

Template Files

adding Apply calls

adding diagram Apply calls

changing for project

modifying

Sequencer Process

Temporal Expressions

expressing with Parameters

Test Bench

compiling

generating

simulating

Test Reader

Test Vector Files

defining class fields with

format

TestBencher Project

design flow

TestBuilder

enabling integration

Third-Party Simulators

time

Time 0

Time Break Markers

TimeOut

Timing Diagrams (see Diagrams)

Transaction

Timeout

Transaction Diagrams

overview

sequencing

Transaction Generator

Transaction Manager

file format

in TestBuilder

in VHDL

run modes

Transactor Overview

transactorBfmPath

Triggering Order of Parameters and Markers

- U -

UART

unsigned_int

unsigned_logic

Use Clauses (VHDL)

User Defined Type

- V -

Variable

Definition of Types and properties

Variables

creating

Diagram Variables

editing

exporting signal states to a file

Overview

Project - accessing in Verilog

Project Variables

random with constraints

State Variables

storing samlped values in

Verbose Samples, Delays, Markers, Sensitive Edges

Verbose Transaction Logging

Verilog

accessing project variables

VeriLogger Project

converting to TestBencher

VHDL

Libraries

Post Calls

Use Clauses

View Source Code

generated for diagrams

View Variables

- W -

Wait Semaphore Marker

Wait Until Marker

Waiting For State Transitions

Waveforms

driving with variables

waveperl.log

Weightings Table

While Loop Markers

Window Samples

add to diagram

definition