SynaptiCAD Tutorials

(Sim) 2.5 Simulate VHDL test bench using ModelSim

(Sim) 2.5 Simulate VHDL test bench using ModelSim

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(Sim) 2.5 Simulate VHDL test bench using ModelSim

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First map the standard syncad library, syncad_vhdl_lib, so that ModelSim can locate it in this project (this step requires that you have previously compiled the syncad library as described at the beginning of this tutorial). This step only needs to be done once for a project. Next, run the simulation and generate the vcd results file, you can either use the ModelSim do script included with this tutorial or manually type the commands.

Map SynaptiCAD library to ModelSim:

Launch a DOS command prompt and type the following commands:

cd \synapticad\project\add4

vmap syncad_vhdl_lib C:\Synapticad\lib\vhdl\modelsim_vhdl_lib


EITHER run the do script to simulate, by typing from the command prompt:

copy c:\Synapticad\Examples\TutorialFiles\Waveformer2MsimVHDL\ .

modelsim -do

OR type the following individual commands below

1.        To generate library files:

vlib work

2.        To compile the source files:

vcom add4.vhd add4test.vhd

3.        Select the top level module to simulate (this will launch the ModelSim GUI):

vsim testbench

4.        In the console window of the ModelSim GUI, set the name of the vcd dump file:

VSIM> vcd file add4.vcd

5.        Specify the signals to dump to the vcd file (top level signals in the design):

VSIM> vcd add /testbench/*

6.        Simulate the design+stimulus

VSIM> run –all

7.        Exit the simulator (the vcd file will be created by ModelSim at the end of this step):

VSIM> quit –f