SynaptiCAD Tutorials

(TBench) 3.7 Add a Sample to Verify Data

(TBench) 3.7 Add a Sample to Verify Data

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(TBench) 3.7 Add a Sample to Verify Data

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Next a Sample will be added to the read timing diagram. Samples compare the actual state value of an input signal to the expected state value, and conditionally react to the results of the comparison.

Add the sample:

In the tbread diagram, press the Sample button so that right clicks will add samples.


First, left-click on the third falling edge (250ns) of CLK to select the edge.

Then, Right-click near the end of the blue valid segment on DBUS.


This adds a Sample parameter named SAMPLE0 that lines up with the third neg edge of the CLK signal.

Investigate the sample code generation features:

The default behavior of the sample compares the run time value with the drawn value ($$data) and throws an Error if they are different. This is the behavior that we need for the tutorial. The next few steps show you the HDL code generation dialog and how to control the generated code. You do not need to make any changes to the dialog defaults.

Double-click on the sample name SAMPLE0 in the drawing window to open the Sample Properties dialog.

Notice that this dialog controls all of the display features for the Sample. The sample can be offset from the triggering edge. Also notice that the HDL Code Generation is enabled.

Press the HDL Code button to open the Code Generation Options dialog.


The Sample generates an code in the form of if/then/else.

Look through the condition and action drop-downs to see the built-in behavior choices.

Make sure to return the dialog to the shown state so that error messages will be generated if the Sampled data does not match the variable.


Press OK to close the Code Generation Options dialog. Then press OK to close the Sample Properties dialog.

Save the timing diagram by selecting File > Save Timing Diagram from the main TestBencher menu.