2.13 Project Window Overview

The Project window is used to control the files that get simulated and to display debugging information about a design during simulation. This section highlights some of the main topics and provides links where these topics are covered in more detail.

Setting up a Project

•Create a project and learn the basic navigation features of the tree ( Step 3: Create a Project )

•Add source code files to a project ( Step 4: Add Source Files to the Project )

•Set or change the model under test to be instantiated inside an auto-generated test bench ( Step 5: Draw a Test Bench (optional) )

•Build a project and set the top level components to simulate ( Step 6: Build the Project and Set the top )

•Force a source code file to compile to a destination library ( 2.2 Build and Simulate )

•Setting a new Stimulus and Results File and archiving off that file and the loge file ( 3.1 Stimulus and Results Diagram )

Simulation and Debugging Features

•Add watch signals to a diagram ( 2.3 Watching Signal and Component Waveforms )

•Add condition breakpoints to break on signal changes ( 2.4 Breakpoints )

•View and edit signal state values ( 2.5 Inspect And Edit Values )

•View driver tree for a signal to analyze design data flow ( 2.6 Find Drivers )

•Set the simulator's interactive scope by right clicking on an instance ( 4.3 Navigating Code with the Project Window )

Navigating and Finding things within the Project Window

•View source code library files found via library search paths ( 2.9 Source Code Libraries )

•View compiled libraries ( 2.10 Compiled Libraries (Symbolic Libraries) )

•View all source code files included by a compiled source code file ( Step 4: Add Source Files to the Project )

•Find source code declarations by double clicking ( 4.3 Navigating Code with the Project Window )

•Use code in an editor window to jump to the object in the Project Window ( 4.3 Navigating Code with the Project Window )

•Search for items in the Project tree ( 4.5 Searching in the Project Window )

Lesser Known Features

•Add source code to instantiate a component in a source code editor window ( 4.4 Fast HDL Code Editing )

•Translate a single VHDL file to Verilog (or vice versa). This feature requires a license for the V2V Verilog/VHDL translator ( 9.1 Graphical Interface for Translation )

•Show Verilog objects in a schematic window. This features requires a license for the Gates-On-The-Fly Verilog netlist editor ( 11.2 Launching the Schematic window )

•Toggle Library Setting for user source files. Library files are compiled with the -v option ( 5.4 Simx Commonly used Command Line Options )

•Dump a component's ports to a timing diagram as Drive (stimulus) signals instead of as Watch signals ( 4.4 Fast HDL Code Editing )