Automatically verifying thousands of connections between PCBs
When developing large electronic systems consisting of multiple Printed Circuit Boards (PCBs), making sure that each signal is connected to the correct pin of a connector is a cumbersome task. Until now there has not been a way to verify these connections automatically and designers were forced to manually check each connector pin. Using ConnTrace you can process a number of netlists (which may be in different formats), define the connections and trace the signals from board to board.
ConnTrace uses rules (based on regular expressions)
to match the signal names between PCBs. It allows the tool to validate
groups of matches although individual signals can still differ. The
rules can be generated automatically and be fine-tuned by the designer.
The automated approach will often match 80% to 90% of all connector pins.
The flexibility of ConnTrace allows it to be used in any design flow and does not require any design methodology. The rule generator in combination with the sorted problem view allows engineers to validate large systems in a few hours.
Once the project and its rules are defined it is a simple task to re-verify the connectors when changed were made to the PCBs. All out-of-date files are processed in one action.
Features & Benefits
- Compare PCB signal/pin names using regular expressions
- Automatic rule generation
- User directed acceptance of verified differences
- Igloo, Igloo+, Iglooe
- One click verification and consistency
- Reports incremental changes in pin- and net list
- Concentrate on a dozen differences instead of a thousand lines
- Fits in any design flow
- HTML report
The figure below is an example of the kind of
connectivity tracing ConnTrace can perform.
ConnTrace will show that:
- A3 is connected to A4 when Brd1 is placed in the system
- A1, A2, A6 are connected to C1, C2 and C6
- A5 and A6 are connected to R3 and R4
- B1 and B2 are connected to R1 and R2
Supported PCB Designs Systems
ConnTrace supports the majority of Schematic Capture / PCB development systems from the leading vendors Altium, Cadence, Mentor Graphics and Zuken. Different formats may be used within a single project.
Most interfaces are based on a netlist generated by the PCB system. If your PCB system is not present please check if it is capable of generating one of the netlists presented below. If you have a netlist format which is currently not supported please contact HDL Works. Adding a new format can often be realized in a short time frame.
- Support by Vendor
- Cadence Design Systems
- Mentor Graphics
- Board Station
- Design Capture
- Support by File Format
- EDIF (Altium, VeriBest)
- Cadence packaged netlist (pstxnet.dat, pstchip.dat)
- Cadence Board file PCB (.brd)
- Cadence Telesis netlist (.tel)
- Zuken RINF netlist (.frs)
- Zuken NDF netlist (.ndf)
- Mentor DxDesigner 'Quick Connection View' (.qcv)
- Mentor Packager cross ref. netlist (.pxr)
- Mentor Board Station netlist (.net, nets.txt)
- PADS ascii database (.asc)
- Windows XP Vista 7/8
- Linux (should work with any recent distribution). Tested with RHEL 5 and Suse 10.1
- Floating time-based license only
Click here to download ConnTrace EASE, HDL Companion, or IO Checker
Would you like a quick walk-through of ConnTrace? Please contact our sales department by phone
540-953-3390 or email email@example.com.