SYNAPTICADcolon TEST BENCH GENERATORS
 

TestBencher Pro

VHDL, Verilog, and TestBuilder Graphical Test Bench Generation

TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches. One of the most time consuming tasks for users of HDL languages is coding test benches to verify the operation of their design. In his book "Writing Testbenches," Janick Bergeron estimates that 70% of design time is spent verifying HDL code models and that the test bench makes up 80% of the total HDL code generated during product development.

TestBencher Pro automates the most tedious aspects of test bench development, allowing you to focus on the design and operation of the test bench. This is accomplished by representing each bus transaction graphically and then automatically generating the code for each transaction. TestBencher makes use of the powerful features of the language that is being generated and the engineer does not have to hand-code each transaction. When hand coding, the designer would have to take the time to deal with the specifics of the design (port information, monitoring system response, etc) as well as common programming errors (race conditions, minor logic errors, and code design problems). This removes a considerable amount of time from the test bench design process because TestBencher manages the low-level details and automatically generates a valid test bench.

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Got a question about TestBencher Pro and HDLs?

Post your question on the newsgroup comp.lang.verilog and it will be answered by our technical support staff (the newsgroup is checked at least once a day). You can always call 800-804-7073 to have any questions answered directly.

Language translations

Japanese: Test Bench Generator

German: Test Bench Generator

French: Test Bench Generator