TestBencher Pro e Support
TestBencher Pro provides designers with a graphical environment for generating e cycle-based or time-based
bus-functional models from language-independent timing diagrams. With TestBencher you can upgrade your
verification flow to include the power of the e verification language. SynaptiCAD joined Verisity's
LicenseE program to build support for the e language into TestBencher Pro. Verisity's e language provides
powerful constructs for handling sequence recognition (temporal events), arbitration, and comprehensive
dynamic coverage analysis that are not available in VHDL or Verilog. TestBencher Pro's graphical interface
speeds up test bench development for both expert and novice users. TestBencher generates all of the
low-level transaction code (TCMs), verification code, sequence detection, error reporting and file I/O
code. The graphical representation also enhances the ability of engineers to share data across projects,
even for new engineers that are not yet familiar with the e language.
TestBencher Pro e Design Flow
TestBencher Pro generates e test benches directly from timing diagrams. The test benches use a bus-functional
model architecture that enables test bench models to be created from data contained in component data
sheets. Additionally, TestBencher's graphical representations and automatic code generation abstract
coding details away from the user. This abstraction reduces the amount of time needed for creating test
benches. Automating what was once a manual and tedious process of developing test benches allows engineers
to focus on the design and operation of the test bench rather than the painstaking aspects of code development.
The generated test benches are compiled with Verisity's Specman Elite and simulated using all major
VHDL and Verilog simulators.
System Level Design
TestBencher Pro generates the entire test bench using the graphical timing diagrams, information extracted
from the model under test, and the top-level test bench file. The only code that the user writes is
at the system-level, all of the other code is automatically generated. In the sequencer process of the
top-level test bench file, the user will specify the order and logic for applying the timing diagram
transaction procedure calls to the model under test. TestBencher can automatically generate the e transaction
code and the data structures needed for the transactions, so users can concentrate on the functionality
of the top-level test-bench. The test bench components created by TestBencher Pro can be easily integrated
into an existing Specman Elite test bench.
Graphical Samples Generate e Temporal Expressions
TestBencher Pro features state and timing protocol checker generation for verifying the response of
the model being tested. TestBencher's sample construct can check the state of a signal at a given point
in time or over a window of time. Samples can also check for either a state change or for stability
during the sampling window. Sample window intervals can be specified as an amount of time or number
of clock cycles (to support cycle-based test bench generation).
Samples are also used to verify a sequence of events. For example, they can be used to synchronize the
diagram to an event on a control signal and then conditionally store data in various types of data targets.
Appropriate e temporal expressions are generated based on the way a waveform is drawn in a sample region.
The sampled data can be used later in the same transaction, other transactions, passed up to the top-level
test bench, or saved to a file.
Advanced e Data Structures Supported
TestBencher Pro also supports various "data sources and targets" that allow the user to easily read
data from and write data to table-formatted files, queues, arrays, and associative arrays. Data sources
and targets enable storage and manipulation of complex data structures that are useful for modeling
packet-based protocols. This feature is particularly useful when generating bus-functional models to
test devices on a communications bus.
TestBencher Pro's Class Definition dialog is used to create user defined structures (e structs) that
can contain queues, arrays, associative arrays, and single elements of basic e types and other structures.
Each field can be optionally defined as random, so that Specman Elite can generate random data to fill
the packet. TestBencher also can create variable declarations (struct members), which can be globally
accessible, local to a transaction, or parameters to a transaction.
Automatically Launch Specman Elite and HDL Simulators
TestBencher Pro can control Specman Elite and external simulators through it's graphical interface,
so that compilation and simulation of the project can be handled without having to exit TestBencher.
This is particularly useful when developing the initial test bench because it allows you quickly run
a simulation, see the results, and modify the test bench all within the same graphical environment.
TestBencher automates the steps for passing Specman Elite the data and code that it needs to compile
the generated test bench. TestBencher creates a make file containing all of the information about your
model under test and the commands to dynamically link to the test bench library. TestBencher then launches
your VHDL or Verilog simulator with this make file. TestBencher stores information about both your simulator
and Specman Elite, and can remotely call those programs and display the results of the simulation.
Other features include automatic port and signal extraction from HDL models, parameterization of both
state and timing values through function call parameters or data files, checkers for signal stability
and/or edge transitions within a window of time, and conditional application of edge transitions based
on these checks.
The innovative combination of TestBencher Pro and Specman Elite delivers a consistent and quick solution
to the most demanding verification problems. This integration allows designers to focus on the verification
of the device under test and not on the implementation of the test bench.