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SynaptiCAD's WaveFormer supports Agilent & Tektronix equipment and Hyperlynx

   June 26, 2013

SynaptiCAD presents IO Checker 2.2, the FPGA and PCB IO verification tool

   March 15, 2013

Timing Diagram Editors Simplify FPGA Synthesis

   December 5, 2012

SynaptiCAD releases HDL Simulator Swapper

   September 5, 2012

VHDL/Verilog Converters upgraded for Verilog 2005

   April 19, 2012

VeriLogger Supports Symbolic Libraries and Runtime Optimizations

   March 22, 2012

SynaptiCAD Speeds Up Free Waveform Viewer

   October 4, 2011

SynaptiCAD's BugHunter Supports C++ and SystemC

   June 23, 2011

TestBencher Simplifies Random Transaction Generation

   March 28, 2011

SynaptiCAD's BugHunter Supports 64-bit ModelSim & Incisive Simulators

   November 11, 2010

SynaptiCAD's GOF fixes Logic Equivalence Check Failures

   September 16, 2010

WaveFormer Lite Generates Mixed Signal Test Benches for all FPGA design flows

   August 11, 2010

VeriLogger supports encrypted models from Actel, Altera, and Xilinx

   July 1, 2010

Timing Diagram Editors offer Editable Analog Equations

   May 25, 2010

SynaptiCAD's 64-Bit Verilog Simulator is 30% Faster

   January 15, 2010

Free High Performance Verilog 2001 simulator

   November 16, 2009

Gates-on-the-Fly Netlist Editor adds Waveform Viewer Interoperability

   October 30, 2009

SynaptiCAD tools import Xilinx timing information

   September 10, 2009

SynaptiCAD Timing Diagram Editors support Sampled Analog Signals

   September 10, 2009

Gates-on-the-Fly Netlist Editor and Schematic Viewer

   August 20, 2009

SynaptiCAD offers HDL Works Tools

   November 10, 2008

V2V Translators get Verilog 2001 Support and Graphical Debugger

   September 15, 2008

Timing Diagram Editors add Mixed-Signal Capabilities

   August 20, 2008

Free VCD Waveform Viewer Gets Faster

   January 28, 2008

SynaptiCAD Acquires V2V Software and offers HDL Translation service

   October 11, 2007

SynaptiCAD upgrades VeriLogger Extreme - version 12

   August 1, 2007

SynaptiCAD upgrades WaveFormer Pro and DataSheet Pro - version 12

   July 12, 2007

SynaptiCAD releases VeriLogger Extreme a new Verilog simulator

   Jan 2, 2007

SynaptiCAD updates Free Waveform Viewer

   May 24, 2006

SynaptiCAD celebrates 14 years of Timing Diagram Editor Development

   November 17, 2005

SynaptiCAD Products Now Available for Linux

   June 3, 2005

University of Washington uses SynaptiCAD's Verilog simulator, 2004 Report

   February 14, 2005

SynaptiCAD and Actel Upgrade Libero IDE With Reactive Test Bench Generation

   January 31, 2005

SynaptiCAD joins graphical debugging market

   April 2, 2004

SynaptiCAD and Pulse Instruments Partnership

   July 16, 2003

DataSheet Pro adds Multiple Timing Diagrams

   MAY 20, 2003

SynaptiCAD releases PinPort - Hardware To Simulation Interface

  DECEMBER 1, 2002

SynaptiCAD Supports TestBuilder Development

  JANUARY 21, 2002

TestBencher Pro generates code for OpenVera

  MAY 25, 2001

TestBencher generates SystemC code

  MARCH 15, 2001

TestBencher Adds Support for Cycle-Based Bus Transactions

  AUGUST 4, 2000

WaveFormer Pro supports Analog Signals and Waveform Comparison

  DECEMBER 15, 1999

OLE-Enabled DataSheet Pro Simplifies Timing Diagram Management

  MAY 22, 1999

 

Articles

Graphical TestBench Generation

WWW.TESTBENCH.IN - Donna Mitchell
Test Benches can be generated from language independent timing diagrams, which are a natural way to design and display the parallel activity that occurs in within test benches.

Easing Today's Verification Language Bedlam

ECN - Donna Mitchell and Dan Notestein
Writing reusable bus-functional testbench models has always been a challenge. In the past few years, several verification languages have been introduced to address that challenge. For a company like SynaptiCAD Inc. (Blacksburg, VA), which makes the TestBencher Pro graphical code generator, a diverse customer base requires that our tool be able to generate the same model in all verification languages currently in use. We have a lot of experience pushing each language to its performance limits and comparing how the languages work.

Timing (Analysis) is Everything: A How-To Guide for Timing Analysis

Circuit Cellar - Philip Nowe
Philip Nowe, a WaveFormer Pro user, describes the importance of timing analysis and some of the techniques and tools available for doing timing analysis. What is timing analysis? Why is timing analysis important? How do you perform timing analysis? Click here to read the paper.

Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++

ICU - Ben Rhodes and Dan Notestein
Techniques for creating Verilog, VHDL, and C++ hierarchical test benches that support re-use at different stages during the design of large-scale systems. Race avoidance, handling of multiple clock domains, lookup techniques for emulating hierarchical references to BFMs in VHDL, emulation of "class-like" data structures in Verilog and VHDL, and the use of a golden reference model to verify functionality while testing a system against constrained-random data are discussed.

Interfacing VHDL and Verilog Designs to C++ Models

ECN - Donna Mitchell
Techniques for automating the process interfacing VHDL and Verilog models to C++ high-level models. Using graphical code generation tools and public domain C++ libraries, engineers can setup a C environment and start simulating in just a few hours.

Testbench grafisch generieren

ElektronixPraxis - Donna Mitchell
German Editorial on how graphical test bench generation facilitates the collaboration of many engineers by removing the need to interpret source code. Includes both English and German translations.

SynaptiCAD generates OpenVera code

Electronic Engineering Times - Richard Goering
Providing some of the first third-party tool support for the OpenVera hardware verification language, SynaptiCAD Inc. has rolled out TestBencher Pro version 7.4, which generates OpenVera testbenches from timing diagrams.

Synapticad testbench generator adds SystemC support

   APRIL 06, 2001

Electronic Engineering Times - Richard Goering
Synapticad Inc. said it is offering the first tool able to generate SystemC testbenches from language-independent timing diagrams. The company's TestBencher Pro 7.2 graphical testbench-generation tool includes support for SystemC, an emerging system-level

A complete list of all papers is on the Technical Papers page.

 

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