Below are reprints of several technical articles
Test Benches can be generated from language
independent timing diagrams, which are a natural way to
design and display the parallel activity that occurs in
within test benches.
Philip Nowe, a WaveFormer Pro user, describes the importance of timing analysis and some of the techniques
and tools available for doing timing analysis. What is timing analysis? Why is timing analysis important?
How do you perform timing analysis? Click here
to read the paper.
ABSTRACT: CThis paper will discuss techniques for creating hierarchical test benches that support re-use
at different stages during the design of large-scale systems. A generic test bench architecture will
be described that can be implemented using either Verilog, VHDL, or the TestBuilder verification library
of SystemC, with notes on techniques required by the quirks of each language. Some of the techniques
that will be covered include race avoidance, handling of multiple clock domains, lookup techniques for
emulating hierarchical references to BFMs in VHDL, emulation of "class-like" data structures in Verilog
and VHDL, and the use of a golden reference model to verify functionality while testing a system against
constrained-random data. Click here to read the
ABSTRACT: C++ models add many new capabilities to Verilog and VHDL simulations including the ability
to use high-level data structures, constraints, and random data generation. C++ models are also very
useful for co-simulation of hardware and software. Despite the advantages of C++ models they have been
relegated to simulation of large systems because of the cost associated with setting up the C++ environment.
New techniques are now available to automate the process so that C++ models can by used by anybody.
Using graphical code generation tools and public domain C++ libraries, engineers can setup a C++ environment
and start simulating in just a few hours. Click here
to read the paper.
ABSTRACT: System-level designers have been using C and C++ for many years to model large systems, but
generally hardware designers have avoided them, instead using hardware description languages such as
Verilog and VHDL. This is because hardware description languages (HDL) are generally better at modeling
hardware at the register transfer level and gate level, and C++ is better for modeling high-level behavior
such as that used in bus-functional models. However, hardware design complexity is increasing because
more system-level functionality is being implemented in hardware to increase system performance. This
is forcing hardware designers to look more closely at languages such as C++ that excel at behavior-level
modeling so that they can begin modeling their system earlier in the design cycle. New languages and
tools for modeling hardware in C++ and connecting C++ models to HDL models have recently emerged that
reduce the learning curve and development time for creating mixed C++/HDL designs. This article examines
some of the benefits of C++ based models and how new tools decrease the time to create and use them.
Click here to read the paper.
ABSTRACT: This article was intitally featured in Design & Elektronik a German trade magazine,
and titled Ein Bild sagt mehr als tasuend Worte. Verification design complexity will force many
of you to reconsider your current methods of creating test benches. But the available choices are difficult
to evaluate. Will you stick with a modeling language like VHDL, Verilog, or SystemC? Or will you switch
to one of the new verification languages such as OpenVera or the "e" language? Whatever choice you make,
you are still faced with the problem of developing complex test benches, and maintaining that code over
the course of several projects and possibly several verification engineers. Graphical code generation
offers a language independent solution to test bench development that enables engineers to quickly describe
test benches in a manner that is clear and precise. Click here
to read the paper.
ABSTRACT: This article was intitally featured in the Chip-Design section of ElektronikPraxis
a German trade magazine. This is an Editorial describing how graphical test bench generation facilitates
the collaboration of many engineers by removing the need to interpret source code. Includes both English
and German translations. Click here to read the paper.
ABSTRACT: This article was intitally featured in the Soft Copy section of ECN Magazine. Verification
design complexity will force many of you to reconsider your current methods of creating test benches.
But the available choices are difficult to evaluate. Will you stick with a modeling language like VHDL,
Verilog, or SystemC? Or will you switch to one of the new verification languages such as OpenVera or
the "e" language? Whatever choice you make, you are still faced with the problem of developing complex
test benches, and maintaining that code over the course of several projects and possibly several verification
engineers. Graphical code generation offers a language independent solution to test bench development
that enables engineers to quickly describe test benches in a manner that is clear and precise. The paper
is available in HTML and
ABSTRACT: This article was intitally featured in the Soft Copy section of ECN Magazine. Designers
are looking for new methods to reduce verification time for both simulation models and hardware prototypes.
In many ways both of these environments suffer from the same problems of test vector creation, test
coverage, analysis of results, and detection of elusive timing problems. There are many EDA tools and
hardware test systems available to help solve these problems in each environment, but in the past there
has not been a way to leverage the work done in one environment into the other. In this paper, we propose
several techniques that unite the worlds of simulation and hardware verification and which take advantage
of strengths offer by each environment. Click here to read the
Listen to a taped slide presentation by SynaptiCAD and Agilent Technologies that will demonstrate how
you can use EDA tools and measurement equipment to assist you in making further reductions in the design
time for your products and help you get to market a lot sooner. For instructions on loading the net
seminar click here.
Getting the best performance out of your silicon means squeezing every little bit of extra time out
of your circuit. One way to improve system speed is to perform a delay correlation analysis during the
early stages of your design and optimize your circuit to take advantage of the delay tracking between
gates. The variation in delays between gates within a given IC is smaller than between gates on different
ICs of the same type because of process and temperature variations across the ICs. Delay correlation
between on-chip gates gives designers the ability to build circuits that can run faster than might seem
possible when performing timing analysis using the worst case across-chip min/max delays provided by
most chip manufacturers.
Experienced digital designers have been taking advantage of delay correlation for many years to build
high speed circuits, but until recently there has been no tool for systematically designing a circuit
that optimizes system timing by accounting for delay correlation effects. SynaptiCAD's WaveFormer program
enables a designer to interactively specify and analyze delay correlation effects on system timing as
his design takes shape, allowing the designer to visualize the true timing bottlenecks in his system
and make system changes to achieve optimal system performance. Click here
to read the paper online.
ABSTRACT: This article was initially featured in the Soft Copy section of ECN magazine. It
explains the purpose, history, and design applications of the new TDML (Timing Diagram Markup Language)
standard. The TDML format was developed to address the current compatibility problems in EDA tools.
In addition to this, TDML will provide a way for semiconductor manufacturers to distribute timing information
via the internet. Click here to read the paper online.
ABSTRACT: This article discusses the importance of top down timing analysis, how it differs from back-end
timing analysis methods such as post-layout static timing analysis and back-annotated timing simulation,
and how a designer performs top down timing analysis. Also discussed are the benefits of using a timing
diagram editor to perform top-down timing analysis. Click here to read the paper
online or Download article in Acrobat
ABSTRACT: Describes how to write simple VHDL test benches by hand and how to automatically generate
them using WaveFormer. This was published as an appendix in a book called VHDL Made Easy by David Pellerin.
Click here to read the paper
ABSTRACT: Describes some of the technical problems that WaveFormer helps digital engineers overcome.
Topics include: timing diagram generation, temporal equation signal generation, reconvergent fanout,
and stimulus generation for VHDL. Click here to read the paper