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Taking Advantage of Delay Correlation Effects to Design High Speed Digital Circuits

by
Peter Menegay, Ph.D.
Daniel L. Notestein, M.S.

Abstract

Getting the best performance out of your silicon means squeezing every little bit of extra time out of your circuit. One way to improve system speed is to perform a delay correlation analysis during the early stages of your design and optimize your circuit to take advantage of the delay tracking between gates. The variation in delays between gates within a given IC is smaller than between gates on different ICs of the same type because of process and temperature variations across the ICs. Delay correlation between on-chip gates gives designers the ability to build circuits that can run faster than might seem possible when performing timing analysis using the worst case across-chip min/max delays provided by most chip manufacturers.

Experienced digital designers have been taking advantage of delay correlation for many years to build high speed circuits, but until recently there has been no tool for systematically designing a circuit that optimizes system timing by accounting for delay correlation effects. SynaptiCAD's WaveFormer program enables a designer to interactively specify and analyze delay correlation effects on system timing as his design takes shape, allowing the designer to visualize the true timing bottlenecks in his system and make system changes to achieve optimal system performance

Introduction

One of the most important initial steps in digital design is to perform a preliminary timing analysis to determine if the system can be designed to meet performance requirements. Without it, no circuit can proceed from the conceptual phase. Even with it, most errors in design occur because of timing mistakes. The traditional method of timing analysis, pencil and paper, quickly overwhelms a design engineer, especially for a large circuit. Fortunately, the recent past has seen the emergence of software which automates the construction of complex timing models. The user is now able to optimize a design relatively quickly, without having to redraw the entire diagram each time a tweak is made.

The critical data entered into a timing diagram is the delay times and operating constraints of the system components. These timing parameters are generally expressed as a range (e.g. 5-10 ns) because there is some uncertainty associated with high volume component manufacture and circuit operating conditions. To combat these uncertainties in component delays and constraints, designers have traditionally been forced to assume worst case operating conditions that are overly pessimistic with regard to maximum operating speed. This is because the probabilities associated with these ranges are generally treated as independent quantities.

It is known that components placed on the same circuit have a correlation between their delay times. If one component has an actual delay time at the high end of its uncertainty range, others on the same circuit will tend to be at the high end also. This idea forms the basis for narrowing the delay time uncertainty and, with appropriate design techniques, enables circuit speed-ups.

Delay correlation will be reviewed by first defining the concept and then showing, through specific examples, how it can enhance circuit design. Some mathematical and algorithmic problems associated with it will be discussed. It will become apparent that computer solution is vital for properly handling delay correlation.

Delay Correlation Defined

Delay correlation is simply a relationship between two propagation delays (or more) in a circuit. Slide 3 illustrates this formally. If one delay can be expressed as a function of the other, then some correlation between them is said to exist. This function is normally piecewise linear and expressed in terms of a correlation factor (or percentage) between 0-1.

Although it is unnecessary to construct the exact functional relationship, it is instructive to see how delay correlation affects a specific delay. If, somehow, we are given a certain delay within an interval, the equations on slide 4 show how the second interval is a function of the first interval and the delay correlation. The max and min functions serve only to ensure that the delay range never exceeds the maximum and minimum absolutes given by the physical component. From the equations it is apparent that correlation serves to narrow the interval over which the delay can occur. For no correlation (cf = 0), the interval simply reduces to the absolute limits [a2 , b2].

Delay correlation thus serves to decrease the overall uncertainty difference between delays. If one delay is known to be at the high end of its range, then the other will be at the high end as well. As with the delay ranges themselves, the exact correlation to use is based on component vendor information.

Design Example: Circuit 1

Consider the simple circuit shown in slide 5 comprised of two gates and some range of delay times. Let.s assume that D1 lies in the range 5-10 ns and CLKDELAY2 lies in the range 0-5 ns. If the two gates have no delay correlation (the usual assumption) then the actual delay times for each could fall anywhere in the shown ranges. For instance, if D1=10 ns, then CLKDELAY2 could have a delay time as low as 0 ns. We will call this condition 0% correlation.

At the other end of the spectrum is 100% correlation. This means that if D1=5 ns, then CLKDELAY2=0ns. If DO=7.5ns then CLKDELAY2 will be at 2.5ns, and so forth. Clearly 100% correlation greatly reduces the difference between the two delays. The numbers shown here can be arrived at through the equations on slide 4. However, for these simple cases, visual inspection is easier.

What happens for, say, 80% correlation? If D1=5 ns, then CLKDELAY2 will be in the range 0-1 ns. In other words the possible range for CLKDELAY2 spans 20% (100% - 80%) of its total range. Now, if D1=10 ns, then CLKDELAY2 would have a range of delay times from 4-5ns. This is because the CLKDELAY2 range is .20% around 5ns, it.s corresponding point. Obviously, since a higher delay time than 5 ns is not possible, the range is 4-5 ns rather than 4-6 ns.

Slide 6 shows a timing diagram for this case with 0% correlation. The table below the diagram makes reference to a required setup time of 5 ns. Since the actual setup time equals 5 ns, the margin, or slack time is 0 ns.

However, with correlation the slack time would increase, as shown in slide 7. Here we generate a table showing the possible intervals for CLKDELAY2 given each D1 in the range 5-10 ns. By inspection of the timing diagram (or circuit itself) a simple formula can be written to be solved for slack time. It is important to note that this formula is a function of the difference between the two correlated delays. By inspection of the table we find the minimum (most negative) difference between CLKDELAY2 and D1. When inserted into the formula for SLACK we arrive at the most conservative estimate for the slack time. As expected, the higher the correlation, the higher the slack time.

Clearly, an increase in slack time allows an increase in clock frequency. Going from 0% to 100% delay correlation would allow an increase in clock frequency from 40 MHz to 50 MHz, a 20% increase. For 80% correlation a 47 MHz clock would be permissible, still a sizable increase. Use of delay corrrelation can significantly impact circuit speed.

It can also be shown for this example a timing failure which disappears when the effect of delay correlation is introduced. To illustrate this, consider the reverse of the above case, a 50 MHz clock initially with the case of no correlation. Since the margin was zero with the 40 MHz clock, this case will certainly fail. However, as we just saw, the case is successful if the delay correlation is known to be 100% and properly accounted for. Thus, delay correlation can correct pessimistic calculation errors which might cause a good circuit design to be rejected.

Another example based on the same circuit illustrates a potential benefit of clock delay and shows how delay correlation can correct a possible failure in the timing verification. Suppose that the delay time interval for D1 is increased to 12-17 ns. In a worst case scenario (0% correlation), D1 would be 17 ns and CLKDELAY2 would be 0 ns. The total path from the clock through D1 is then 27 ns (CLKOUT1+D1). Since the available clock time is 25 ns (CLKPERIOD+CLKDELAY2), the clock would be clocking the input signal to FF2 when it was still low (ie, before it had a chance to change to the correct high value for this cycle). However, for 80% correlation, if CLKDELAY2 were 0 ns, then D1 would be at 13 ns and the clock would be seeing a correct high input signal. This is a result which could only be achieved by first having clock delay, and second making use of delay correlation.

Design Example: Circuit 2

Our second example is a slightly more complex version of the first employing, in addition, a return loop and a clock delay for FF1. Slide 8 provides a schematic. The return loop with D2 provides an additional constraint on the system, illustrated in slide 9. Any time increase in the D1 path will reduce the time available to the D2 path.

The equations in slide 9 help make this point. Assume the system has no slack time. Then, if D1 is increased, CLKDELAY1 must decrease by an equal amount. This causes less time available for the D2 path, and D2 must decrease a corresponding amount to make up for this deficiency.

This effect is important because it can arise when making use of delay correlation to get more time through one path. A designer must keep in mind that in most practical circuits, gains in one path will be offset by losses in other paths.

Slide 10 shows the effect of correlation between the two clock delays. As with the previous example, the clock period is affected by delay correlation. For a worst case analysis a clock period 4 ns higher must be specified than the case where we can count on 80% correlation between the delays.

Design Example: Circuit 3

A further example is illustrated in slide 11. This case is similar to circuit 2 except we assume that one path is much longer than the other. Furthermore we suppose that we can locate the clock generator such that it falls very close to FF1, very close to FF2, or somewhere in the middle. This amounts to saying the clock is on the left, right, or middle, respectively. We assume that located on the left the clock delay to FF1 will be zero, on the right the clock delay to FF2 will be zero, and in the middle the clock delay to either flip flop will be split evenly.

The first question is where to locate the clock to achieve maximum clock frequency. The timing equations shown in slide 12 indicate that if we place the clock on the right side, the required clock period would have to be greater than or equal to 35 ns. Slides 13-14 go through the same procedure for the clock located on the left and in the middle. Slide 15 summarizes the results by showing that the lowest clock period occurs if the clock is located on the left side. Incidentally, this result contradicts many engineering assumptions which would place the clock in the middle in an attempt to minimize the difference in clock arrival times at the flip-flop clock inputs.

Despite correctly locating the clock, by using delay correlation we can improve even more on our specification of the clock period. Slide 15 shows that if CLKDELAY is correlated 100% with D1A and D1B (as if they were a single delay) the specified clock would need to have a period greater than or equal to only 20 ns. Thus, in order to achieve an optimal solution, the clock must be placed in the correct location and delay correlation effects should be accounted for.

Multiple Path Delay Correlation

So far the examples have treated cases in which there were two correlated delays in a circuit. In reality, however, each circuit under consideration will have many delays and correlation factors may exist between any two delays or group of delays. This situation makes the timing analysis considerably more complex.

Consider the figures shown in slide 16. In the first case we have three gates, each having some correlation to the other two. We assume for simplicity that the delay interval for all the gates is 0-10 ns. Furthermore let.s assume that the delay for gate 1 is known with certainty and is equal to 0 ns. Since gate 2 is 100% correlated with gate 1, it also has a delay of 0 ns. Now, since gate 3 is 30% correlated with gate 2, its delay range is in the interval 0-7 ns. However gate 3 also has 90% correlation with gate 1, making its delay interval 0-1 ns. Which is the correct interval to choose for gate 3? The answer is the one that satisfies all the other constraints. If 0-7 ns is chosen, then it is conceivable for gate 3 to have a delay outside the interval 0-1 ns (the constraint imposed by the 30% correlation). Therefore the correct choice is 0-1 ns, since it will always satisfy the other constraint.

The second example of slide 16 shows a case with four gates. Now we must choose the correct correlation for gate 2 and gate 4. We do so in the same manner. However, it is easy to see that by increasing the number of gates the problem quickly becomes too complex to do by visual inspection. Virtually any gate on a circuit can be correlated with any other gate, or group of gates. The only restriction is that no two gates can have more than one correlation between them. This problem necessarily lends itself to computer solution.

Mathematical Problem/Solution

In the preceding examples it should be noted that the effect of delay correlation on a timing analysis is through the difference between the two delays. Slide 18 states the problem of calculating these differences more formally. In essence, given a correlation factor and two delay intervals, we are interested in the minimum possible difference between the two delay intervals, and the maximum possible difference. This gives us the limits on the range of possible differences.

The solution to the problem is given on slide 19. Although it involves just a series of simple algebraic steps, many such calculations are required for a real design. Again, computer solution is recommended.

Conclusions and Recommended Resources

Delay correlation effects play an important role in timing analysis for digital circuits. Properly accounting for them can both lead to an increase in clock speed and prevent timing analysis errors. Unfortunately delay correlation is too infrequently used in most analyses, forcing designers to use overly pessimistic delay information.

Given the complexity of a real timing analysis problem using delay correlation, computer solution is the ideal way to proceed. SynaptiCAD.s line of timing analysis tools properly computes the effect of delay correlation for any digital design problem.

WaveFormer Pro.s timing diagram editor is an ideal tool for beginning a delay correlation based timing analysis. It.s basic features include a modeless drawing and editing environment; delays, setups, and holds for performing any timing analysis; time markers; seven graphical waveform states; virtual and group buses; clocks with formulas; as well as a variety of ways to document the resulting work. You can automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. Entry of correlation data into WaveFormer is simple. Any delay combination can be specified along with its correlation. Correlation data is then automatically accounted for during subsequent analysis. An option exists to turn off correlation data for any delay combination, effectively making the correlation 0%.

In addition to being a timing diagram editor, WaveFormer Pro has a stimulus generator and an interactive HDL simulator. These features allow the user to automatically generate and simulate timing diagrams using common Boolean and registered logic equations. It can also import or export waveforms to VHDL,Verilog, HP's logic analyzers & pattern generators, SPICE, ABEL, and a variety of gate level simulators. These import capabilities also aid in the acquisition of delay correlation data.

Author Biographies:

Peter Menegay is a Senior Research Engineer, where he is the lead designer for SynaptiCAD's WaveFormer Pro product. Menegay received his Ph.D in engineering from Virginia Polytechnic Institute and State University, and comes to SynaptiCAD from a research position at Dupont. Menegay's industry experience includes over 6 years of hardware and software modeling experience.

Daniel L. Notestein is president of SynaptiCAD Inc., where he directs and performs research and development in elec­trical design automation software and object-oriented framework technology. Notestein received his BS degree in electrical engineering and minors in computer science and math from Virginia Polytechnic Institute and State University and an MS degree in electrical engineering from the University of Texas at Arlington. Notestein worked as a software design engineer and a hardware design engineer at Texas Instruments and Burr-Brown Corporation before founding SynaptiCAD in 1992.

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