Product Update Press Release, September 16, 2010
SynaptiCAD's GOF fixes Logic Equivalence Check Failures
SynaptiCAD's Verilog netlist editor,
Gates-on-the-Fly (GOF), has recently been updated to
support easy correction of logic equivalence failures
introduced during modifications to post-synthesis
netlists, using equivalence check reports from either
Cadence's Conformal LEC or Synopsys's Formality.
SynaptiCAD has also published a white paper,
Gates-on-the-Fly fixes Logic Equivalence Check Failures,
that describes how the
updated GOF was used to find and fix failures indentified
by Cadence's Conformal tool at a customer site.
GOF graphically analyzes and edits large
Verilog netlists that have been generated from a synthesis
or layout tool. Netlists sometimes require changes to
either meet timing closure specifications, fix functional
logic bugs, or to repartition a design. Using GOF's unique
"incremental schematic" technology, you can easily find,
view, and edit specific logic cones in your design on a
schematic to visualize just the paths you need to see
without unnecessary clutter.
For more information on Gates-on-the-Fly see the Gates-on-the-Fly Product Page.
Pricing and Availability
Gates-on-the-Fly is available on Windows
and Linux. A perpetual license sells for $5000 on Windows.
Leasing options are also available. For more information,
contact SynaptiCAD at phone (540)953-3390, fax (540)953-3078, email: firstname.lastname@example.org,
For any questions concerning this press
release please contact Donna Mitchell at 540-953-3390 or
email at email@example.com. High-resolution images can be
downloaded directly from SynaptiCAD's web site at