External Simulator Control
TestBencher Pro can control external simulators through it's graphical interface, so that compilation
and simulation of the project can be handled without having to exit TestBencher. This is particularly
useful when multiple tools are needed to compile and simulate a project. For example, if you are using
one of the new verification languages you will need a tool to compile the test bench into either a dynamically
linked library or byte code. You will also need a VHDL or Verilog simulator and a make file containing
all of the information about your model under test and the commands to dynamically link to the test
bench library. With TestBencher, all of these details are automatically handled for you. TestBencher
stores information about both your simulator and verification compiler and can remotely call those programs
and display the results of the simulation.
Automatically Launch External Simulators
When the external program integration feature is enabled, TestBencher employs the user
specified programs to handle the compilation and simulation of the project. The simulator settings are
saved for each language independently so that it is easy to build and simulate a test bench in different
- Automatically launches ModelSim and sends commands to the graphical interface to display
the test bench control and status signals.
- Graphical integration and control of VCS, VERA, and Verilog-XL using TestBencher's simulation
- Automatic launching of Microsoft's C++ and GNU compilers for SystemC and TestBuilder
- Remote execution of VCS and Vera running on different computers and even under different
operating systems. This means you can use a Windows PC as your desktop machine and transparently run
your simulations as batch jobs on a Solaris box.
Simulator settings are saved for each language individually, so that you can (for instance) simulate
OpenVera projects with VCS and VHDL projects with ModelSim, without having to change the settings each
time you switch between languages.