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What is a test bench?

A test bench is VHDL or Verilog code which generates input stimulus for a circuit.

After a VHDL or Verilog circuit model is written, it must be tested to verify correct operation. To do this, the designer provides the simulator with a set of input signal transitions (stimulus vectors) to exercise the circuit. These stimulus vectors are usually grouped together in an entity called a test bench. Grouping the stimulus vectors together in an isolated entity provides a means to reuse the stimulus vectors as the VHDL or Verilog code for the circuit changes (e.g. as the simulation models are changed from behavioral models to structural models).

When you simulate complex circuits, test benches also must become more complicated. Providing just simple stimulus vectors is not enough. The test benches also start to include extra code to check and see if the outputs of the simulation are correct. Also, the test bench is required to respond to the outputs of the simulation and provide different test vectors depending on the state of the circuit. Once the test bench starts to watch and respond to the circuit state it becomes a model of the environment in which the circuit will eventually operate in. Poor or incomplete test bench design means that the circuit under test will have a poor chance of being error free.


Why might you want to use TestBencher Pro instead of writing a test bench by hand?

Surveys of VHDL users have indicated that generation of VHDL test benches typically consumes 35% of the entire front-end ASIC design cycle. It is clear that automation of test bench generation would significantly reduce the costs of VHDL-based design. TestBencher Pro provides an automated way for generating test benches. Some of the benefits of using TestBencher Pro are:

Entering stimulus vectors in an HDL is time consuming and error prone Writing a VHDL or Verilog test bench is one of the most tedious and error prone parts of the simulation process. In HDLs you are required to specify the time for each signal transition. It is easy to make mistakes when writing an HDL test bench, because it is difficult when viewing the stimulus vectors in textual form to visualize the temporal relationships between transitions on different waveforms. For example it is difficult to tell if a signal transition on one signal occurs before or after a signal transition on another signal. However if you were to draw the signals then the order of signal transitions would be obvious. TestBencher Pro provides a timing diagram editor that allows you to generate waveforms by five different methods: point and click drawing, parameter-based generation of clock signals, temporal equations, Boolean equations of existing signals, and (for especially complex waveforms such as modulated waveforms used in DSP applications) script-based waveform generation. The complete testbench is described using an optimum combination of graphical constructs and text.

Verify simulated system matches original design specification
The first step in most designs is to create a specification of how the system should function. This usually involves the creation of timing diagrams that describe the interaction of the system with the outside world. These timing diagrams can be entered in TestBencher Pro and used to generate test benches for the design implementation (model under test). These test benches can be used to verify that the design implementation performs as originally specified.

Timing diagrams created in TestBencher Pro serve as reuseable library
A test bench created by TestBencher Pro consists of interacting timing diagrams. Each timing diagram describes a different transaction cycle (e.g. memory read/write cycles, PCI bus transaction, etc). Variables can be embedded in the diagrams, creating parameterized diagrams capable of driving different data values on the buses within the diagram. These parameterized diagrams are maintained in a library for reuse in other projects.


How is TestBencher Pro different than other automatic test bench generators?

Users Can Customize the Generation of Test Bench Code VHDL and Verilog are powerful languages that offer a wide variety of ways to generate effective test benches and designers often require customized code in their test benches. The lack of customization in existing test bench generation products is one of the biggest stumbling blocks in the acceptance of test bench tools by ASIC designers.

TestBencher Pro performs its test bench generation by executing Perl scripts (Perl is a standard text processing language that compiles on the fly when a script is executed). This is a unique feature of TestBencher Pro that allows users to customize the code generated by the program. SynaptiCAD ships the Perl script source code with TestBencher Pro so that users can alter the way the program generates test bench code. Using TestBencher Pro a user can modify the standard SynaptiCAD scripts to produce exactly the code required for his/her application.

Generate Waveforms in TestBencher Pro using Boolean and Temporal equations
Many waveforms are difficult to draw (e.g. a waveform that alternates between a frequency of 25Mhz and 50Mhz every 20 cycles). These types of waveforms can be described in TestBencher Pro using temporal and boolean equations. The waveform described above could be generated using the following temporal equation: CK25_50 ( (20=H 20=L)*20 (10=H 10=L)*20 ) *5

Waveforms can also be expressed in terms of other signals in a diagram using a boolean equation. For example: ENB = (CEB or WEB) delay 10 would create a signal called ENB that was the boolean ORing of signals CEB and WEB delayed by 10 nanoseconds.

TestBencher Pro supports gate-level and transistor-level simulators
Timing diagrams generated in TestBencher Pro can also be used to produce test vectors for gate-level and transistor-level (SPICE) simulators. This means you can create stimulus once and use it in several different simulation environments.


What is the difference between WaveFormer and TestBencher Pro?

SynaptiCAD has two different products that generate test benches for VHDL and Verilog. Our first product, WaveFormer generates simple test benches that consist of waveform stimulus for VHDL, Verilog, and gate level simulators like Viewlogic, Mentor, and OrCAD. TestBencher Pro is a super set of WaveFormer and adds the capability to describe self-testing test benches which interact with the module under test during simulation. Both products contain a complete timing diagram editor and the Perl engine.