SYNAPTICADcolon TEST BENCH GENERATORS
 

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TestBencher works with ALM's Advanced Chip Verification

SynaptiCAD and American Logic Machines have worked together so that TestBencher Pro can generate test benches for ALM's Advanced Chip Verification (ACV) kit. The ACV is capable of generating complex real world transactions that will verify your design. TestBencher Pro generates test vectors for the ACV kit using graphical timing diagrams.

System Level Features

The ACV kit provides an inclusive verfication environment that takes into account inter-chip and external interfaces. For example an SOC design may include PCI, GPIO, I2C, AMBA, etc. Thus your test suite will require a spectrum of test vectors. The test vectors for each bus can vary from a simple read cycle to a complex multi cycle transactions. For exhaustive testing, the ACV-kit also gives you the capability of generating a massive amount of transaction data and conditionally injecting errors to check the robustness of your design. The results of using the ACV kit in "saved engineering time" is unprecedented, followed by the added benefit of early chip completion.

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