SYNAPTICADcolon TEST BENCH GENERATORS
 

TestBencher Pro OpenVera Support

TestBencher Pro provides designers with a graphical environment for generating OpenVera cycle-based or time-based bus-functional models from language-independent timing diagrams. With TestBencher you can upgrade your verification flow to include the power of the OpenVera hardware verification language. OpenVera provides powerful constructs for handling sequence recognition, arbitration, and comprehensive dynamic coverage analyses that are not available in VHDL or Verilog. TestBencher Pro.s graphical interface speeds up test bench development for both expert and novice users. TestBencher generates all of the low-level transaction code, verification code, sequence detection, error reporting and file I/O code. The graphical representation also enhances the ability of engineers to share data across projects, even for new engineers that are not yet familiar with the OpenVera language.

TestBencher Pro OpenVera Design Flow

TestBencher Pro generates OpenVera test benches directly from timing diagrams. The test benches use a bus-functional model architecture enables test bench models to created from data contained in component data sheets. Additionally, TestBencher's graphical representations and automatic code generation remove, or abstract, coding details away from the user. This abstraction reduces the amount of time needed for test bench generation. Automating the most tedious aspects of test bench development allows engineers to focus on the design and operation of the test bench rather than the painstaking aspects of code development. The generated test benches are compiled with the Synopsys.s VERA tool and simulated using all major VHDL and Verilog simulators.

System Level Design

TestBencher Pro generates the entire test bench using the graphical timing diagrams, information extracted from the model under test, and the top-level test bench file. The only code that the user writes is at the system level; all of the other code is automatically generated. In the sequencer process of the top-level test bench file, the user will specify the order and logic for applying the timing diagram transaction procedure calls to the model under test. TestBencher can automatically generate the transaction code and the OpenVera data structures needed for the transactions, so users can concentrate on the functionality of the top-level test-bench.

Graphical Samples Generate OpenVera Expects

TestBencher Pro features state and timing protocol checker generation for verifying the response of the model being tested. TestBencher.s sample construct can check the state of a signal at a given point in time or over a window of time. Samples can also check for either a state change or for stability during the sampling window. Sample window intervals can be specified as an amount of time or number of clock cycles (to support cycle-based test bench generation).

Samples are also used to verify a sequence of events. For example, they can be used to synchronize the diagram to an event on a control signal and then conditionally store data in various types of data targets. OpenVera restricted, simple, and full expects are generated based on the way the waveform beneath a sample is drawn. The sampled data can be used later in the same transaction, other transactions, passed up to the top-level test bench, or saved to a file.

OpenVera Advanced Data Structures Supported

TestBencher Pro also supports various .data sources and targets. that allow the user to easily read data from and write data to table-formatted files, queues, arrays, and associative arrays. Data sources and targets enable storage and manipulation of complex data structures that are useful for modeling packet-based protocols. This feature is particularly useful when generating bus-functional models to test devices on a communications bus.

TestBencher Pro.s Class Definition dialog is used to create OpenVera User Defined Types (UDTs) which can contain queues, arrays, associative arrays, and single elements of basic OpenVera types and other UDTs. Each field can be optionally defined as random, so that the OpenVera randomize function can fill the packet with data. Each field can also be defined as static so that one memory location is shared by several instances of the class. OpenVera.s Mailboxes are used to implement queues, so all of the functionality of Mailboxes is made easily accessible.

TestBencher generates the code for the definitions and instances of these UDTs and basic OpenVera types. The instances can also be created as a queue, array, or associative array. Variables can also be created locally within a particular transaction.

Other Features

Other features include automatic port and signal extraction from HDL models, parameterization of both state and timing values through function call parameters or data files, checkers for signal stability and/or edge transitions within a window of time, and conditional application of edge transitions based on these checks.

"We wanted to upgrade our verification flow to include the power of the new verification languages like OpenVera, but we were reluctant to incur the down time necessary to learn the language. Then we discovered TestBencher Pro's graphical verification environment and were impressed with the speed in which we could quickly develop a VERA test bench," said Cecil Stone, senior verification engineer at Lucent Technologies. "Also TestBencher Pro's language independent timing diagrams let us quickly generate Verilog test benches to perform timing tests on the same models."

Summary

The innovative combination of TestBencher Pro and VERA delivers a consistent and quick solution to the most demanding verification problems. This integration allows designers to focus on the verification of the device under test and not on the implementation of the test bench.