Advanced Gate Representation

The Boolean Equation edit box in the Signal Properties dialog can accept several advanced operators, such as conditional expressions and signal concatenation. These operators can be used to model multiplexers, tristate gates, and multi-bit signal. Here we will demonstrate several of these advanced modeling techniques.

Conditional Expressions for Multiplexers and Tristate Gates

The C language conditional expression of conditional ? if_expr : else_expr can be used inside the Boolean Equation edt box to model multiplexers and tristate gates.

Some examples are:

Tristate Gate EnableSIG ? SIG0 : `bz
2-1 MUX S0 ? SIG0 : SIG1
4-1 MUX S1 ? (S0 ? SIG0 : SIG1) : ( S0 ? SIG3 : SIG2)

Multi-bit Equations

Multi-bit equations are specified by setting the MSB and LSB of the signal (loacated at the bottom of the signal propertities dialog). To change a simple 1-bit equation to a 4-bit equation, change the MSB of the signal involved to 3.

Concatenation of Signals

Concatenation of signals is supported using the Verilog concatenation operator
{ exp_1 ,  expr_2 } . Set the MSB in the signals properties dialog to the proper size. If the size of the concatentated signal is larger than the receiving signal, then the most significant bits are dropped.

Some examples of the concatenation operator:

Signal Concatenation {SIG0,SIG1}
Concatenating bit-slices {SIG0[3:0],SIG1[7:4]}

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