Version 8.0 Features

SynaptiCAD is proud to release version 8.0 of our product line. Version 8.0 is the largest single update ever to our software and represents the work of 16 full time programmers working over a period of 12 months. Below is a list of features that have been added to each of our products.


TestBencher Pro generates test benches from graphical timing diagrams.

VHDL and Verilog Support

  • New C++ based library integration using the open TestBuilder libraries.
  • Constrained Random Data generation with TestBuilder support.
  • Temporal Equations with TestBuilder support.
  • Automatic generation of TestBuilder-style test benches.

OpenVera Support

  • Support for generation of data structures like arrays, associative arrays, and queues.
  • Data packing support for advanced data structures
  • Constrained random data support through a graphical interface in the data structures dialog.
  • Remote execution of VCS and VERA running on different computers and even under a different operating system. This means you can use a Windows PC as your desktop machine and transparently run your simulations as batch jobs on a Solaris box.

SystemC Support

  • Automatic compilation of SystemC test benches using either Microsoft's C++ compiler or GNU GCC compiler.

External Simulator Control
When the external program integration feature is enabled, TestBencher uses the specified programs to handle the compilation and simulation of the project.

  • Automatically launches ModelSim and sends commands to the graphical interface to display the test bench control and status signals.
  • Graphical integration and control of VCS, VERA, and Verilog-XL using TestBencher's simulation button bar.
  • Automatic launching of Microsoft's C++ and GNU compiliers for SystemC and TestBuilder code.
  • Remote execution of VCS and Vera running on different computers and even under different operating systems. This means you can use a Windows PC as your desktop machine and transparently run your simulations as batch jobs on a Solaris box.
  • Simulator settings are saved for each language individually, so that you can (for instance) simulate OpenVera projects with VCS and VHDL projects with ModelSim, without having to change the settings each time you switch between languages.

Data Structure Features

  • Variables can be scoped at the diagram level as well as the top level.
  • Complex data structures can be passed as parameters to a bus transaction.

Sample Features

  • Samples can function in a blocking or non-blocking mode. Blocking samples cause a transaction to pause its execution until the condition it waits for occurs.
  • Samples can optionally store a state value depending on whether their if condition is true or false.
  • Severity level of sample logging levels is individually controllable. Four levels of logging are supported: Note, Warning, Error, and Failure. The highest level, Failure, causes a simulation run to be halted.

Top-Level Test Bench Control

  • Project Wizard simplifies creating new test benches.
  • Model Under Test is automatically instantiated in the top-level test bench.
  • Multiple instantiation of TestBencher projects, allowing you to build system-level test benches using a bottom up approach.
  • Switch between cycle-based and time-based versions of a test bench with the click of a button.
  • Graphical port editor for modifying a project component's ports.
  • Template Diagram feature allows the user to specify a template of a diagram that is used when creating new diagrams in a given project. The most common usage of template diagrams is to extract the port information from your model under test into the template diagram so that all future diagrams you create in that project will already contain the model's port signals.
  • Project tree interface organizes the different components of the test bench into separate folders on the project tree.

Signal State Features

  • Signal state values can be specified as full expressions including Boolean equations that reference state variables and user-defined data structures.
  • Signal states can contain conditional expressions that determine at run-time what value to drive based on the value of other variables in the simulation.
  • Boolean equations are more language independent, further simplifying conversion of a test bench from one target language to another.


VeriLogger Pro is a Verilog simulator with built-in graphical test generation.

PLI and XEMACS Editing Support

  • Improved PLI support and documentation.
  • Complete editing/debug integration with the popular XEMACS editor (available on Unix and Windows).

C++ Library Support

VeriLogger is tightly coupled with a new TestBench++ library. This is a C++ library derived from Cadence's TestBuilder(R) library that has been ported to work on Windows as well as UNIX. This library brings many new capabilities to VeriLogger, including:

  • Powerful C++-style file I/O functions
  • Advanced data structure support already written including: associative arrays, priority lists, stacks, queues, priority queues, bags, and sparse arrays.
  • Constrained random data generation
  • Fully dynamic process creation for easier modeling of order indeterminate systems.
  • Support for temporal assertions/temporal expressions
  • Easy connection between C++ system reference models and HDL RTL-level models for advanced test bench verification.
  • This library is supported on Solaris and Microsoft Windows.

All the new WaveFormer Pro features are also in VeriLogger Pro


DataSheet Pro provides documentation professionals with an integrated environment for working with multiple timing diagram documents.

View Support

  • Image views for creating multiple pictures from one timing diagram file are now easier to use and more powerful.
  • Image views can be used to quickly change how a section of a timing diagram is displayed in addition to how it is printed.
  • OLE images update in the containing application as soon as you make a change in our timing diagram editor.

All the new WaveFormer features are also in DataSheet Pro.


WaveFormer combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a rapid prototyping EDA tool that helps you design faster with fewer mistakes.

VCD Import Features

  • Over 50x improvement in load times for VCD files.
  • Ability to convert signals to "clock" signals.
  • Improved performance of Waveform comparison functionality (optional).

Static Timing Analyzer Support

  • Import support for Synopsys's TimeMill(R) analog waveform format.

Test Equipment Support

  • Import support for Agilent's LogicWave logic analyzer waveform format.

All the new Timing Diagrammer features are also in WaveFormer Pro.


Timing Diagrammer Pro is a powerful, feature-laden timing diagram editor that lets you analyze your design in the early stages, before you have a schematic.

Graphical Drawing Environment

  • Multiple edges can be selected and moved in lock step.
  • Multiple timing parameters, markers, text objects, and edges can be selected as a group and deleted.
  • The Insert and Delete clock cycles functions have the option to adjust the edge times of all signals clocked off the clock being modified. This is particularly useful when modifying bus transactions. This new functionality is the default behavior.
  • Increased performance of many GUI operations when working on large files. For example, undo and redo times have been dramatically reduced for large files.
  • Automatic radix conversion functions make it easy to display waveform data in different radixes.

GigaWave Option

The GigaWave Option increases the waveform handling capacity by over 200x.

  • GigaWave Option can be added to any of SynaptiCAD's products.
  • Increased waveform handling capacity (approximately 200x, depending on the data).
  • New binary waveform format (.btim) for super fast loading and storing of large waveform data sets (.btim files load several hundred times faster than their equivalent VCD file).

Comparison Option

The Comparison Option graphically displays the differences between compared waveforms for two timing diagrams or individual signals.

  • Comparison Option can be added to any of SynaptiCAD's products.
  • This feature is exceptionally useful when comparing two different simulation runs, as well as for comparing logic analyzer data to a simulation run.
  • The Comparison Option supports both event-based and clock edge-based comparisons, and tolerance ranges that provide a method for screening out small differences that do not affect circuit operation.
  • This option also provides a tool bar for moving between the differences in a diagram.

OLE Option

OLE option allows interactive timing diagrams to be embedded directly into data sheets.

View Support

  • OLE option is a standard feature in DataSheet Pro, and it can be added to any of our other products.
  • Image views for creating multiple pictures from one timing diagram file are now easier to use and more powerful.
  • Image views can be used to quickly change the how a section of a timing diagram is display in addition to how it is printed.
  • OLE images update in the containing application as soon as you make a change in our timing diagram editor.