SynaptiCAD's WaveFormer supports Agilent & Tektronix equipment and Hyperlynx wf_translation_v18.png - 53k
VeriLogger Supports Symbolic Libraries and Runtime Optimizations - version 17 vextreme_design_flow.jpg - 53k
SynaptiCAD's BugHunter Supports C++ and SystemC bughunter_with_systemc_big.jpg - 127k
TestBencher Simplifies Random Transaction Generation pr_testbencher_with_random_transactions_big.jpg - 88k
SynaptiCAD's BugHunter Supports 64-bit ModelSim & Incisive Simulators bughunter_64bit_support_big.jpg - 185k
SynaptiCAD's GOF fixes Logic Equivalence Check Failures pr_gof_lec_sep_2010.jpg - 181k
WaveFormer Lite generates Mixed-Signal Test Benches for all FPGA design flows wfl_mixed_signal_test_bench_big.jpg - 580k
Timing Diagram Editors offer Editable Analog Equations wfm_block_wqn_big.jpg - 145k
SynaptiCAD's 64-Bit Verilog Simulator is 30% Faster verilog_simulator_watching_sigs_big.jpg - 117k
Free High Performance Verilog 2001 simulator verilogger_extreme_1_editor_main_big.jpg - 160k
Gates-on-the-Fly Netlist Editor adds Waveform Viewer Interoperability gof_waveformviewer_big.jpg - 234k
Timing Diagram Edtitors support Xilinix - main timing diagram image Timingdiagram_cover_online_big.jpg - 160k
Timing Diagram Edtitors support Xilinix - with new View feature timing_diagrams_with_views_big.jpg - 127k
Gates-on-the-Fly Netlist Editor and Schematic Viewer: main viewer window image gof_main_netlist_viewer_big.jpg - 303k
Gates-on-the-Fly Netlist Editor and Schematic Viewer: schematic window image gof_schematic_netlist_analyzer_eco_big.jpg - 549k
SynaptiCAD offers HDL Works Tools SynaptiCAD_distributes_HDLworks.jpg - 197k
V2V Translators get Verilog 2001 Support and Graphical Debugger v2v_interface_lines.jpg - 256k
Timing Diagram Editors add Mixed-Signal Capabilities Pr_wfp_v13_mixed_signal_support_timing_diagram.jpg - 100k
Free VCD Waveform Viewer Gets Faster gigawaveviewer_waveform_viewer_flow.jpg - 108k
SynaptiCAD Acquires V2V Software and offers HDL Translation service v2v_pr_big.jpg - 52k
SynaptiCAD upgrades VeriLogger Extreme - version 12 Fast Verilog Simulation pr_v12_wfp_dsp.jpg - 201k
SynaptiCAD upgrades WaveFormer Pro and DataSheet Pro - version 12 faster rendering and more graphical features pr_v12_wfp_dsp.jpg - 302k
SynaptiCAD releases VeriLogger Extreme - high performance Verilog simulation vextreme_design_flow.jpg - 53k
SynaptiCAD updates Free Waveform Viewer pr_syncad_waveviewer_v11.jpg - 200k
SynaptiCAD celebrates 14 years of Timing Diagram Editor Development pr_td_v10_image.jpg - 100k
SynaptiCAD and Pulse Instruments Partnership pi2005_wf_designflow.jpg - 80k
DataSheet Pro adds Multiple Timing Diagrams multiplediagrams.tif - 180k
SynaptiCAD Supports TestBuilder Development syn_tb8_printimage.tif - 178k
TestBencher Pro generates code for OpenVera tb_openvera.gif - 39K
TestBencher generates SystemC code tbp_design_flow.gif - 89K
TestBencher Adds Support for Cycle-Based Bus Transactions tb7_testbench_automation_tool.png - 36K tbcycle_87.gif - 71K tb7_editor_image.gif - 13K
WaveFormer Pro supports Analog Signals and Waveform Comparison wfpv65.gif - 60K
SynaptiCAD syn_logo_hr.gif - 38K syn_logo.FH9 - 37K
TestBencher Pro tbp_logo_hr.gif - 15K tbp_logo.FH9 - 22K
VeriLogger Pro vlp_logo_hr.gif - 15K vlp_logo.FH9 - 22K
WaveFormer Pro wfp_logo_hr.gif - 16K wfp_logo.FH9 - 21K
DataSheet Pro dsp_logo_hr.gif - 15K dsp_logo.FH9 - 22K
TimingDiagrammer Pro tdp_logo_hr.gif - 21K tdp_logo.FH9 - 24K
GigaWave Viewer gigawave_vcd_viewer_huge.png - 19K gwv_logo.FH9 - 22K
G Series gserieslogo_hr.png - 5K g_series_logo.FH9 - 19K
TestBencher Pro G Series tbp_gserieslogo_hr.png - 20K tbp_gseries_logo.FH9 - 24K
VeriLogger Pro G Series vlp_gserieslogo_hr.png - 20K vlp_gseries_logo.FH9 - 24K
WaveFormer Pro G Series wfp_gserieslogo_hr.png - 20K wfp_gseries_logo.FH9 - 24K
DataSheet Pro G Series dsp_gserieslogo_hr.png - 19K dsp_gseries_logo.FH9 - 24K
TimingDiagrammer Pro G Series tdp_gserieslogo_hr.png - 25K tdp_gseries_logo.FH9 - 26K
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