SYNAPTICADcolon
 

WaveFormer Pro and HP Logic Analyzers

A Success Story from IBM

Measuring Long Term Reliability of SDRAMs on a System Motherboard

by Dan Notestein, SynaptiCAD Sales, Inc.

One of the more difficult tasks in the production of digital systems is ensuring reliable system operation for long periods of time under potentially adverse environmental conditions. While working at IBM in Research Triangle Park, North Carolina, Arnold Motley turned to SynaptiCAD's WaveFormer Pro and Hewlett Packard's 16700 Logic Analysis System to test the reliability of synchronous DRAMs being used in IBM's line of workstations as well as its Aptiva personal computers.

"Modern personal computers and workstations routinely operate continuously for days, weeks, and even months. Even one failure in trillions of cycles is generally unacceptable for many applications. A bad memory read or write operation on a workstation handling monetary transactions could turn a routine money transfer into a financial disaster", says Motley.

IBM purchases SDRAMs from many manufacturers and it needed a way to rate the reliability of different vendors’ chips both for purchasing decisions and to provide feedback to the memory vendors on lot quality. The ultimate measure of reliability in this case was how well the chips performed on the actual motherboards.

To test operation under these conditions, Motley used the HP 16555 logic analyzer card in the HP 16700 to capture data from the SDRAM over its different cycles (read, write, mode register set, and refresh) in real world operating conditions. To probe the pins of the SDRAM module, he used the SDRAM DIMM probe and bus extender produced by FuturePlus Systems. The logic analyzer was configured to capture  two megabytes of waveform data as soon as the first setup or hold violation was detected. This waveform file was then loaded into SynaptiCAD's WaveFormer Pro for further analysis. WaveFormer Pro's ability to specify and check for setup and hold violations between pairs of signals was then used to generate a report of setup and hold violations between the captured signals. This report served as a measure of the reliability of the SDRAMs in terms of the number of violations detected in the waveform dump file.

"Creating reports of all the timing violations would have been totally impractical without WaveFormer", Motley explains. "I would have had to visually check for timing violations between several dozen signals over the entire two megabyte data file. Using WaveFormer made analyzing the data quick and easy."

Under the Hood: How WaveFormer Performs Continuous Setup and Hold Checking

WaveFormer can import waveforms from many sources (gate-level simulators, HDL simulators, and logic analyzers) into its own internal format. WaveFormer then converts this data, along with user-entered setup and hold requirements, into a Verilog source code file and an SDF (Standard Delay Format) file containing the timing constraints to be checked. These files are automatically fed to WaveFormer’s internal Verilog simulation engine. The waveform results from the simulation run are captured in the waveform viewing window, and a simulation log file called verilog.log is displayed in the report window. The simulation log file contains status information about the simulation run, including a report of the times and conditions under which any specified setup or hold violations were detected.

"The use of a Verilog simulation engine to detect timing violations really gives you a lot of flexibility," adds Motley. "In this case, all the timing constraints were specified at the interface to the SDRAM where all the pins could be probed, but when you’re designing with PLDs, the constraints are usually specified on internal registers where the signals being checked are some Boolean function of the inputs on the pins. The ability to simulate parts of the internal circuitry of the device comes in really handy in these cases since you can’t probe the signals directly, but hand coding a Verilog model would be kind of a pain. WaveFormer’s point and click interface for entering registered logic equations really simplifies this process."