Multi-bit equations are specified by setting the MSB and LSB of the signal
(loacated at the bottom of the signal propertities dialog). To change a simple 1-bit equation
to a 4-bit equation, change the MSB of the signal involved to 3.
Concatenation of Signals
Concatenation of signals is supported using the Verilog concatenation operator
. Set the MSB in the signals properties dialog to the proper size. If the size of the concatentated
signal is larger than the receiving signal, then the most significant bits are dropped.
Some examples of the concatenation operator: