v2vh_tap.hdl

--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: tap.v
-- Tool Version: verilog2vhdl  v2.41_1  Thu Oct 12 11:16:15 EDT 1995  
-- Date Created: Fri Nov 10 11:20:56 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tap IS
PORT (SIGNAL \out\ : OUT std_logic;
      SIGNAL \_enable_\ : OUT std_logic;
      SIGNAL \register\ : OUT std_logic;
      SIGNAL \re$etn\ : OUT std_logic;
      SIGNAL \***shift***ir***\ : OUT std_logic;
      SIGNAL \with\ : OUT std_logic;
      SIGNAL clock_ir : OUT std_logic;
      SIGNAL \shift+dr\ : OUT std_logic;
      SIGNAL \clock_\ : OUT std_logic;
      SIGNAL \capture__dr\ : OUT std_logic;
      SIGNAL \abs\ : OUT std_logic;
      SIGNAL \now\ : IN std_logic;
      SIGNAL tck : IN std_logic;
      SIGNAL \in\ : IN std_logic);
END tap;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF tap IS
USE Verilog.functions.all;
USE Verilog.timing.all;
SIGNAL \V2V_out\ : std_logic;
SIGNAL \V2V__enable_\ : std_logic REGISTER ;
SIGNAL \V2V_register\ : std_logic;
SIGNAL \V2V_re$etn\ : std_logic REGISTER ;
SIGNAL \V2V_***shift***ir***\ : std_logic REGISTER ;
SIGNAL \V2V_with\ : std_logic;
SIGNAL V2V_clock_ir : std_logic;
SIGNAL \V2V_shift+dr\ : std_logic REGISTER ;
SIGNAL \V2V_clock_\ : std_logic;
SIGNAL \V2V_capture__dr\ : std_logic;
SIGNAL \V2V_abs\ : std_logic;
SIGNAL D : std_logic REGISTER  := '1';
SIGNAL C : std_logic REGISTER  := '1';
SIGNAL B : std_logic REGISTER  := '1';
SIGNAL A : std_logic REGISTER  := '1';
SIGNAL inhi : std_logic;
SIGNAL tckd : std_logic;
SIGNAL NA : std_logic;
SIGNAL NB : std_logic;
SIGNAL NC : std_logic;
SIGNAL ND : std_logic;
SIGNAL GRST : std_logic;
SIGNAL GSIR : std_logic;
SIGNAL GSDR : std_logic;
SIGNAL GENB : std_logic;
SIGNAL \buffer\ : std_logic;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   WAIT UNTIL posedge(tckd) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      \V2V_re$etn\ <= '0';
      WAIT FOR 0 ns;
   ELSE
      \V2V_re$etn\ <= to_stdlogic(GRST);
      WAIT FOR 0 ns;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tckd) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      \V2V__enable_\ <= '0';
      WAIT FOR 0 ns;
   ELSE
      \V2V__enable_\ <= to_stdlogic(GENB);
      WAIT FOR 0 ns;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tckd) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      \V2V_***shift***ir***\ <= '1';
      WAIT FOR 0 ns;
   ELSE
      \V2V_***shift***ir***\ <= to_stdlogic(GSIR);
      WAIT FOR 0 ns;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tckd) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      \V2V_shift+dr\ <= '1';
      WAIT FOR 0 ns;
   ELSE
      \V2V_shift+dr\ <= to_stdlogic(GSDR);
      WAIT FOR 0 ns;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tck) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      D <= '1';
      WAIT FOR 0 ns;
   ELSE
      IF to_boolean(tck = '1') THEN
         D <= TRANSPORT to_stdlogic(ND) AFTER 1 ns;
      END IF;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tck) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      C <= '1';
      WAIT FOR 0 ns;
   ELSE
      IF to_boolean(tck = '1') THEN
         C <= TRANSPORT to_stdlogic(NC) AFTER 1 ns;
      END IF;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tck) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      B <= '1';
      WAIT FOR 0 ns;
   ELSE
      IF to_boolean(tck = '1') THEN
         B <= TRANSPORT to_stdlogic(NB) AFTER 1 ns;
      END IF;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   WAIT UNTIL posedge(tck) OR posedge(inhi);
   IF to_boolean(inhi = '1') THEN
      A <= '1';
      WAIT FOR 0 ns;
   ELSE
      IF to_boolean(tck = '1') THEN
         A <= TRANSPORT to_stdlogic(NA) AFTER 1 ns;
      END IF;
   END IF;
END PROCESS;
\re$etn\ <= \V2V_re$etn\;
\_enable_\ <= \V2V__enable_\;
\***shift***ir***\ <= \V2V_***shift***ir***\;
\shift+dr\ <= \V2V_shift+dr\;
\buffer\ <= to_stdlogic((\now\));
inhi <= to_stdlogic(NOT (\in\));
tckd <= to_stdlogic(NOT (tck));
\V2V_register\ <= to_stdlogic((A) AND (B) AND (C) AND (D)) AFTER 2 ns;
\V2V_out\ <= to_stdlogic(D);
V2V_clock_ir <= to_stdlogic(NOT (NOT A AND B AND D AND tckd));
\V2V_with\ <= to_stdlogic(A AND NOT B AND C AND D AND tckd);
\V2V_clock_\ <= to_stdlogic(NOT (NOT A AND B AND NOT D AND tckd));
\V2V_abs\ <= to_stdlogic(A AND NOT B AND C AND NOT D AND tckd);
\V2V_capture__dr\ <= to_stdlogic(NOT A AND B AND C AND NOT D);
NA <= to_stdlogic(NOT (NOT (NOT \buffer\ AND (NOT C AND 
      A)) AND NOT (\buffer\ AND NOT B) AND (NOT (\buffer\ 
      AND NOT A) AND NOT (\buffer\ AND (C AND D)))));
NB <= to_stdlogic(NOT (NOT (NOT \buffer\ AND (B AND NOT 
      A)) AND NOT (NOT \buffer\ AND NOT C) AND NOT (NOT 
      \buffer\ AND (NOT D AND B)) AND NOT (NOT \buffer\ 
      AND (NOT D AND NOT A)) AND NOT (\buffer\ AND (C AND 
      NOT B)) AND NOT (\buffer\ AND D AND (C AND A))));
NC <= to_stdlogic(NOT (NOT (C AND NOT B) AND NOT (C AND 
      A) AND NOT (\buffer\ AND NOT B)));
ND <= to_stdlogic(NOT (NOT (D AND NOT C) AND NOT (D AND 
      B) AND (NOT (NOT \buffer\ AND (C AND NOT B)) AND NOT 
      (NOT D AND C AND (NOT B AND NOT A)))));
GRST <= to_stdlogic(NOT (A AND B AND (C AND D)));
GSIR <= to_stdlogic(NOT A AND B AND (NOT C AND D));
GSDR <= to_stdlogic(NOT A AND B AND (NOT C AND NOT D));
GENB <= to_stdlogic((GSIR) OR (GSDR));
\out\ <= \V2V_out\;
\register\ <= \V2V_register\;
\with\ <= \V2V_with\;
clock_ir <= V2V_clock_ir;
\clock_\ <= \V2V_clock_\;
\capture__dr\ <= \V2V_capture__dr\;
\abs\ <= \V2V_abs\;
END VeriArch;