- $ -

$$FillerSignal

- A -

Accolade

Actel Analog Signals

Active low signal name

Advanced PLD

Advanced Register and Latch Controls

Agilent

exporting to fast binary & pods

Logic Analyzer - general

Logic Analyzer - specific

Oscilloscope - general

Oscilloscope - specific

Pattern Generator - general

Pattern Generator - specific

transfering files

Aldec

Aligning bus edges

ALTERA stimulus

analog signals

Capacitor generation

Expontial generation

exporting to SPICE

generating

importing to SPICE

properties

Ramp generation

resample waveform

Sine wave generation

Attach to closest signal

Attach to current time

Attach to edge

Attach to segment

Auto Save feature

Auto Save for Recovery

Autosplit long signal names

- B -

base time unit

batch mode

compare properties

merge properties

Bin() Label Equation

Binary Timing Diagram Format

Binding and unbinding bus edges

bit-slices drawn waveforms

Block Copy Waveforms dialog

blue

Boolean equations

with delays

BTIM format

btimtwf.xs

Bus menu overview

Buses

Add Bus Dialog

aligning edges

binding and unbinding edges

converting signals to

converting Virtual to Group

Differential Signals

Group Buses

Overview

Search bus states

Simulated Buses

Virtual Buses

- C -

Capacitor Charge

Capacitor Discharge

Capilano

CGM metafiles

Change All Instances control

Check for Updates menu

Chronology

clocks

buffer delay

converting from signals

converting to signals

correlating buffer delays

creating

deleting cycles

duty cycle

edge jitter

grid lines

inserting cycles

invert

offset

period formulas

reference clocks

skew and delay correlation

Color Controls for Signals

colors

command line

compare signals and diagrams

clocked compare

compare buttons

Differences File

Differences Tab

display limit

don't care regions

force a compare

grouping

ignoring glitches

interleaving

overview

tolerances

contents

Copy and Paste

Copy Signals menu

correlation

buffer delays on clocks

delay groups

skew between clocks

CSD file type

Curved Arrow

Cut

Cyclize Signals menu

- D -

DataSheet Pro

Dec() Label Equation

delay formulas

Delay Properties dialog

delays

clocked

colors, black, blue, green

creating

formatting

Delete Cycles menu

delete mode

delta button

delta mark

Design Preferences dialog (renamed General Preferences)

DesignWorks

Diagram Merge Properties

Diagram Simulation Preferences dialog

diagrams

copying to clipboard

creating

HDL code generated

multiple views

printing

Diagrams, more than one

Dialog

Copy and Paste

Edit Formula Macro

Parameter Library Preferences

View Parameters in Libraries

Differences Tab

Differential Signals

Display Signal States

display time unit

Drag-Drop Load Timing Diagram

Draw line from marker to edge

Drawing Preferences dialog

Auto place Setups/Holds on lower signals control

Show Direction Icons

Transparent Text Object Background

Drive type

Duplicated Parameter Names dialog

Duty cycle of clock

Dynamically Sized Signals

- E -

Edge Properties dialog

min and max delays

setup & hold min, max, margin

Edge Sensitivity

Edge Time Transition

Edit

Redo

Undo

Edit Clock Parameters dialog

Edit Formula Macro dialog

Edit menu overview

Edit Text and Edge Grids dialog

Edit Text dialog

Shapes

Text Controls

Edit Waveform Edges dialog

End Diagram Markers

Enforce as Sampling Period

EPS files

equations

Boolean

equations for parameters and clocks

Exit Loop When Markers

Exponential waveform

export

Agilent Pattern Generator stimulus

ALTERA stimulus

scripts

SPICE stimulus

STIL Test Vectors

Tektronix Pattern Generator stimulus

tri-state enable signals

VCD files

Verilog stimulus

VHDL stimulus

Export menu overview

exporting to Agilent Pattern Generator

exporting to Tektronix Pattern Generator

Agilent Pattern Generator stimulus

- F -

Falling Edge Sensitivity

fast scrolling

File menu overview

File() Label Equation

FillerSignal

Filter Files

Fonts

Japanese

non-English

For Loop Markers

free parameters

Fusion Analog Signals

- G -

General Preferences dialog

multiple delay resolution

Glitches

gray

green

grid lines

Grid Lines on Signals

grid settings

Grides for aligning Text and Edges

Group buses

- H -

HDL code

HDL Code Markers

Hex() Label Equation

Hide Selected Signals menu

hide signal

High Voltage Threshold

Highlighted regions

hold formulas

Hold parameters

holds

continuous

creating

formatting

HP Logic Analyzer

transfering files

HP Pattern Generator

transfering files

HSPICE

- I -

Ignoring Glitches

Image files in diagrams

Image View Capture dialog

images

copying

copying to clipboard

embedding into documents

FrameMaker

Microsoft Word

MIF

multiple views

OLE

types

WMF

import

Agilent Logic Analyzer - specific

Agilent Oscilloscope - specific

from spreadsheets

scripts

SPICE stimulus

Tektronix Logic Analyzer data

Import Waveforms

General Instructions

Inc() Label Equation

IncString() Label Equation

Infiniium

Insert Cycles menu

Instruction Set Definition

Interleave Signals

on Compare

on Merge

Invert clock

- J -

Japanese

- L -

label equations

Label Font

Label Window Size

libraries

waveforms

Libraries menu overview

Line Type

LINUX

Copy and Paste

Logic Analyzer

Tektronix - specific

Logic Analyzer Import

Agilent

Logo files in diagrams

Loop End Markers

Low Voltage Threshold

- M -

Macros for Libraries

Macros for Waveforms

Map List () Label Equation

Margin

markers

creating

default label

Display Signal States

Draw line from marker to edge

end diagram

HDL Code

loop markers

pipeline boundary

semaphore

time compression

timebreak

timebreak markers

wait until

MaxPlus II stimulus

measurement

Mentor

menus

Merging diagram

Merge Properties

multiple delay resolution

Mutliple Undo Redo

- O -

object properties

Offset on clock

OLE

OmegaSim

OmegaSim file type

Options menu overview

OrCAD

Oscilloscope Import

Agilent

- P -

Parameter

Conflict

Duplicate

Rename

parameter formulas

parameter libraries

adding libraries

copying referenced parameters

creating

Library specifications

macros

merging into a project

referencing parameters

updating a project

viewing parameters

Parameter Library Preferences dialog

parameters

creating

default label

display settings

endpoint highlighting

free parameters

hiding

libraries

moving end points

Parameter window

samples

Search and Rename

Parameters Properties dialog

Custom control

Display as Curved Arrow control

Outward arrows control

Paste

Pattern Generaltor

Agilent

Pattern Generator

General Instructions

Tektronix - specific

PeakFPGA

PeakVHDL

PeakVHDL or PeakFPGA

Perl

API calls

Pipeline Boundary Markers

PNG images

Pod-A-Lyzer

Pods

exporting to HP fast binary

Protel

PSpice

Pulse Instruments

purple

- R -

Radix

user-defined

Rainbow Signals

Ramp

RandInt() Label Equation

RandomIntegerArray() Label Equation

Range()  Label Equation

Reactive Export

generation

simulation

Read Only mode

Recover data

red

Redo

Reference Clock

regular expressions

Rename Parameters

Rename Signals

Rep() Label Equation

Repeat Loop Markers

Report menu overview

Report window

Resample Waveform

Rising Edge Sensitivity

- S -

samples

clocked

creating

formatting

sampling frequency

Scalar Vector Graphics

scripts

naming

writing

scrolling to different views

Search and Rename dialog

Parameter Names

Signals

Waveform States

searching

selecting

multiple edges

Signal Names

waveform segments

Semaphore Markers

Separators between signals

setup formulas

Setup parameters

setups

continuous

creating

formatting

Shapes

Show Critical Paths menu

Show Default Simulated Signals color

Show Direction Icons

Show Hidden Text

Show Index

Show or Hide Signals dialog

Signal

active low names

Analog examples

Analog Properties

Arrows on Edges

Autosplit long signal names

Boolean equations

clocked

Color

Compare

Compare type

converting from clocks

copy signals

copy waveforms

cyclizing to clock edges

Default Radix

Default Signal name

Direction Icons - control

Direction Icons - meanings

display settings

drawing waveforms

Drive type

Dynamically Sized Signals

edge display

Edge Sensitivity

editing groups of edges

Grid Lines

HDL code

hide and show

Hieght (size ratio)

Justify Signal Names

Label Font

labeling equations

latch

Line Thickness

Line Type

moving

properties

Rainbow Signals

register

rename signals

reordering

Separators

Show Index

Simulate

Simulate type

simulating

Size Ratio

Sort names alphabetically

Sort Signals by Bit Significance

Straight or Slanted

Virtual State Text Alignment

Watch type

waveform equations

with delays

Signal Filter dialog

Signal Properties dialog

Active low name

Compare button

Compare type

Direction

Name

Signal() Label Equation

Signals<->Clocks menu

Simulate type

Simulated buses

simulation

errors

preferences

Report window

Sine wave generation

SinEnd

SinStart

Size Ratio

Skew for clocks

Skip() Label Equation

Sort Selected Signals By Name menu

Sort Signals by Bit Significance menu

Sort Signals By Name

Sort Signals By Name menu

Spacer

Specifying Signal Types for Actel Fusion Analog Signals

SpeedWave

SPICE

export

import

STIL

stimulus generation

Style Sheet dialog

Superimposed Signals

SVG images

Symbolic Name

- T -

table of contents

TDML

TE Property

TE Sequence

Tektronix

Logic Analyzer - general

Logix Analyzer

Pattern Generator

Pattern Generator - general

Test Bench Generation

General Instructions

VHDL/Verilog Specific Instructions

Text

adding

Attach to closest signal

Attach to current time

Attach to edge

Attach to segment

display switching thresholds

editing

Highlighted regions

image and logo files

moving

Shapes

text alignment grid

TIFF images

time button

time compression

time formulas

timebreak markers

Timing Analysis Report

Timing Diagram, drag-drop load

Timing Diagrams, more than one

timing parameters

Tolerance for Compare

TR0 file type

Trademark

Transaction Tracker

Transparent Text Object Background

twf.xs

- U -

Undo

Undo buffer

Undo Delete

UNIX

Copy and Paste

use clauses

Use straight edges

user-defined radix

- V -

VCD

VCD export

Verilog

Import VCD

Verilog general export

Verilog test bench generation

verilog.log

VHDL

libraries and use clauses

VHDL general export

VHDL test bench generation

View menu overview

View Parameters in Libraries dialog

Viewlogic

Views

Viewsim

Virtual Buses

Virtual State Text Alignment

- W -

Wait Until Markers

Watch type

Waveform Comparison

waveform equations

Waveform Library

WaveFormer Lite

design flow

reactive export

upgrade options

waveforms

exporting

importing

Waveperl

about

data types

naming scripts

object properties

regular expressions

writing scripts

waveperl.log

WHI - weak high

While Loop Markers

Window menu overview

Windows, multiple

WLO - weak low

Workview

- X -

Xilinx

XML

- Z -

zooming

zooming to different views