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VeriLogger Extreme FAQ


What is the differance between VeriLogger Extreme and VeriLogger Pro?

VeriLogger Extreme is a high-performance compiled-code Verilog 2001 simulator. VeriLogger Pro is an interpreted verilog 1995 simulator. VeriLogger Extreme is the new simulator featured by SynaptiCAD. VeriLogger Pro is still available for purchase and is still shipped.


Does VeriLogger Extreme include the Bughunter Pro debugger?

Yes, VeriLogger Extreme includes the Bughunger Pro GUI debugger at no extra cost. A command line version of VeriLogger Extreme is also avalable.


Is VeriLogger Extreme just a Verilog simulator?

VeriLogger Extreme with Bughunter Pro is a complete Verilog simulation environment. In addition to a Verilog simulator and waveform viewer, VeriLogger Extreme contains a waveform editor, an interactive simulator for analysis of post-simulation results, a continuous HDL test bench generator, a waveform comparison engine, and a waveform translator. Purchased indivually these products would cost upwards of $30,000 dollars, but VeriLogger Extreme has it all - at one incredibly affordable price. Click here for pricing information.


Does VeriLogger Extreme support SDF and gate-level timing?

Absolutely.


Does VeriLogger Extreme support PLI?

Yes. Both the command line version of VeriLogger Extreme (simx) and the GUI version (BugHunter Pro) support PLI. In fact, we use the PLI interface to connect to the TestBuilder verification library and this is also how our waveform viewing environment communicates with the simulator.


Are strengths supported in VeriLogger Extreme?

Absolutely.


Is there a graphical test bench environment in VeriLogger Extreme?

Yes. VeriLogger Extreme automatically generates a test bench around the top-level module and creates signals in that test bench to drive and watch the top-level module. This makes it easy to test small parts of a design before the design is complete.


Does VeriLogger support TDML?

Yes. All SynaptiCAD products can read and create timing diagrams in the new TDML (Timing Diagram Markup Language) format. Click here for more information on TDML .