VHDL to Verilog translation

Please read the HDL Interoperability FAQ before continuing with the documentation of VHDL2Verilog!

• Product Description
• The V2V Advantage
• Supported Constructs
  • Entities and Architectures
  • Signals, Variables and Constants
  • Generics
  • Component Instantiations
  • Process Statements
  • Concurrent Signal Assignments
  • Sequential Statements
  • List of Unsupported Constructs
• A Translation Example

Testimonial Paper (PDF format) presented at: "IP Based Design 1998 International Workshop on IP Based system-on-chip Design" held in Grenoble, France, December 1998.

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