// Translated into Verilog Armstrong Counter example of HLS benchmarks
// Original source: "Chip Level Modeling with VHDL" by Jim Armstrong (Prentice-Hall 1989)
// Arithmetic counter changed to shift counter to test shift operators

module counter(clk, strb, con, data, cnt);

parameter datapath_width = 15;

input clk, strb;
input [1:0] con;
input [datapath_width:0] data;
output [datapath_width:0] cnt;

reg [datapath_width:0] cnt, lim, index;
reg [3:0] consig;
reg enit, renit, cnte, en;

initial
	cnte = 0; 

/************************* Decoder ********************************/
always @(posedge strb)
	case (con)
		2'b00:  consig = 'o1;
		2'b01:  consig = 'o2;
		2'b10:  begin
			consig = 'o4; enit = 1;
			end
		2'b11: 	begin
			consig = 'h8; enit = 1;
			end
	endcase

always @(posedge renit)  enit = 0;

/********************* Limit Loader *******************************/

always @(negedge strb)
	if ( consig === 'h2 ) lim = data;

/********************  Counter ***********************************/

always @(posedge consig[0]) cnt = 'd 1;
always @(en) 
	if (en) cnte = 1;
	else cnte = 0;
 always @(posedge clk)
    if (cnte)
	if ( consig === 4'b0100 )
		cnt = cnt << 1;
	else if ( consig === 'b1000 && cnt !== 16'b0000000000000001)
		cnt = cnt >> 1; 

/********************  Comparator *********************************/

always @(enit)
	if (enit)
		begin
		en = 1; renit = 1;
		end
	else    renit = 0;

always @(enit or cnt)
	if ( (en == 1) && (cnt == lim) )  en = 1'b0;

endmodule