--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: dff.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:45:07 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
GENERIC (CONSTANT delay_typ : integer := 1;
         CONSTANT delay_max : integer := 2);
PORT (SIGNAL D : IN std_logic;
      SIGNAL clk : IN std_logic;
      SIGNAL Q : OUT std_logic;
      SIGNAL set : IN std_logic;
      SIGNAL le : IN std_logic);
END dff;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF dff IS
USE Verilog.functions.all;
USE Verilog.timing.all;
SIGNAL V2V_Q : std_logic REGISTER ;
SIGNAL d_in : std_logic;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   WAIT UNTIL negedge(clk) OR posedge(set);
   IF set = '1' THEN
      V2V_Q <= '1';
      WAIT FOR 0 ns;
   ELSE
      V2V_Q <= d_in AFTER 10.0 ns;
      WAIT FOR 0 ns;
   END IF;
END PROCESS;
Q <= V2V_Q;
d_in <= (D AND le) OR (V2V_Q AND NOT le) AFTER delay(ns, 1 * 10, delay_typ * 10, delay_max * 10);
END VeriArch;