v2vh_hot_counter.hdl

--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: hot_counter.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:46:28 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY hot_counter IS
PORT (SIGNAL powerup : IN std_logic_vector(1 DOWNTO 0);
      SIGNAL hotout : OUT std_logic_vector(7 DOWNTO 0);
      SIGNAL reset : IN std_logic);
END hot_counter;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF hot_counter IS
USE Verilog.functions.all;
USE Verilog.timing.all;
SIGNAL V2V_hotout : std_logic_vector(7 DOWNTO 0) REGISTER ;
SIGNAL index : std_logic_vector(7 DOWNTO 0) REGISTER ;
SIGNAL init_index : std_logic_vector(7 DOWNTO 0) REGISTER ;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   V2V_hotout <= NULL;
   WAIT UNTIL negedge(powerup(0));
   init_index <= "00000000";
   WAIT FOR 0 NS;

   WHILE init_index < "00001000" LOOP
      V2V_hotout(to_integer(init_index)) <= '0';
      WAIT FOR 0 NS;
      V2V_hotout(to_integer(init_index)) <= NULL;
      init_index <= init_index + "00000001";
      WAIT FOR 0 NS;
   END LOOP;

   WAIT;
END PROCESS;

PROCESS 
BEGIN
   V2V_hotout <= NULL;
   WAIT ON powerup, reset;
   IF to_bitvector(powerup) /= "00" THEN
      index <= "00000000";
      WAIT FOR 0 NS;

      WHILE index <= "00000111" LOOP
         WAIT FOR 10 NS;
         V2V_hotout(to_integer(index)) <= '1';
         WAIT FOR 0 NS;
         V2V_hotout(to_integer(index)) <= NULL;
         IF to_bitvector(index) /= "00000000" THEN
            V2V_hotout(to_integer(index) - "00000001") <= '0';
            WAIT FOR 0 NS;
            V2V_hotout(to_integer(index) - "00000001") <= NULL;
         ELSE
            V2V_hotout(7) <= '0';
            WAIT FOR 0 NS;
            V2V_hotout(7) <= NULL;
         END IF;
         index <= index + "00000001";
         WAIT FOR 0 NS;
      END LOOP;

   ELSE
      IF reset > '0' THEN
         index <= "00000000";
         WAIT FOR 0 NS;

         WHILE index < "00001000" LOOP
            V2V_hotout(to_integer(index)) <= '0';
            WAIT FOR 0 NS;
            V2V_hotout(to_integer(index)) <= NULL;
            index <= index + "00000001";
            WAIT FOR 0 NS;
         END LOOP;

      END IF;
   END IF;
END PROCESS;
hotout <= V2V_hotout;
END VeriArch;