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`casex' and `casez' statements are special purpose case routines provided in the Verilog language for
`dontcare' comparison. VHDL has no direct equivalent, but Verilog2VHDL writes out the equivalent
VHDL for a `casex' or `casez' statement. Each of these statements is translated to an equivalent VHDL
`if' statement and the sequential statements are updated accordingly.