SYNAPTICADcolon TRANSLATION SERVICES V2V
********************************************************************

--

-- File Type:    VHDL 

-- Input Verilog file was: cache.v

-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  

-- Date Created: Thu May 18 15:35:15 1995

--

********************************************************************


LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY cache_coherence IS

GENERIC (CONSTANT INVALID : std_logic_vector(2 DOWNTO 0) := B"000";

         CONSTANT SHARED_1 : std_logic_vector(2 DOWNTO 0) := B"001";

         CONSTANT EXCLUSIVE : std_logic_vector(2 DOWNTO 0) := B"010";

         CONSTANT MODIFIED : std_logic_vector(2 DOWNTO 0) := B"011";

         CONSTANT Cache_Fill : std_logic_vector(2 DOWNTO 0) := B"100";

         CONSTANT start_write_back : std_logic_vector(2 DOWNTO 0) := B"101";

         CONSTANT WaitUntilAllInv : std_logic_vector(2 DOWNTO 0) := B"110");

PORT (SIGNAL new_state : OUT std_logic_vector(2 DOWNTO 0);

      SIGNAL Cache_Sector_Fill : OUT std_logic;

      SIGNAL Invalidate : OUT std_logic;

      SIGNAL AdrRetry : OUT std_logic;

      SIGNAL RMS : IN std_logic;

      SIGNAL RME : IN std_logic;

      SIGNAL WM : IN std_logic;

      SIGNAL WH : IN std_logic;

      SIGNAL SHR : IN std_logic;

      SIGNAL SHW : IN std_logic;

      SIGNAL state : IN std_logic_vector(2 DOWNTO 0);

      SIGNAL READ_DONE : IN std_logic;

      SIGNAL clk : IN std_logic;

      SIGNAL reset : IN std_logic;

      SIGNAL send_abort : IN std_logic;

      SIGNAL write_back_done : IN std_logic;

      SIGNAL AllInvDone : IN std_logic);

END cache_coherence;



LIBRARY Verilog;


ARCHITECTURE VeriArch OF cache_coherence IS

USE Verilog.functions.all;

USE Verilog.timing.all;

SIGNAL V2V_new_state : std_logic_vector(2 DOWNTO 0) REGISTER ;

SIGNAL V2V_Cache_Sector_Fill : std_logic REGISTER ;

SIGNAL V2V_Invalidate : std_logic REGISTER ;

SIGNAL V2V_AdrRetry : std_logic REGISTER ;

SIGNAL present_state : std_logic_vector(2 DOWNTO 0) REGISTER ;

SIGNAL next_state : std_logic_vector(2 DOWNTO 0) REGISTER ;

BEGIN



PROCESS 

BEGIN

   WAIT ON present_state, RMS, RME, WM, WH, SHW, READ_DONE, SHR,
           write_back_done, AllInvDone, send_abort, state, reset;

   V2V_Cache_Sector_Fill <= '0'; WAIT FOR 0 NS; V2V_Invalidate <= "0" ;
       WAIT FOR 0 NS; V2V_AdrRetry <= "0" ; WAIT FOR 0 NS; next_state <= "present_state;" WAIT FOR 0 NS;
        IF to_bit(reset) /="0" THEN next_state <= "state;" WAIT FOR 0 NS;
         ELSE CASE present_state IS WHEN (B"000")>

         IF to_bit(RMS) /= '0' OR to_bit(RME) /= '0' OR to_bit(WM) /= '0' THEN

            V2V_Cache_Sector_Fill <= '1'; WAIT FOR 0 NS; next_state <= "Cache_Fill;" WAIT FOR 0 NS;
             ELSE next_state <= "INVALID;" WAIT FOR 0 NS; END IF; WHEN (B"100")>

         IF to_bit(send_abort) /= '0' THEN

            next_state <= INVALID; WAIT FOR 0 NS; ELSE IF to_bit(READ_DONE) /="0" THEN
             IF to_bit(RMS) /="0" THEN next_state <= "SHARED_1;" WAIT FOR 0 NS; 
             ELSE IF to_bit(RME) /="0" THEN
              next_state <= "EXCLUSIVE;" WAIT FOR 0 NS; ELSE IF to_bit(WM) /="0" THEN V2V_Invalidate <= "1" ;
               WAIT FOR 0 NS; next_state <= "WaitUntilAllInv;" WAIT FOR 0 NS;
             ELSE next_state <= "Cache_Fill;" WAIT FOR 0 NS;
             END IF;
             END IF;
             END IF; ELSE next_state <= "Cache_Fill;" WAIT FOR 0 NS; END IF; END IF; WHEN (B"001")>

         IF to_bit(SHW) /= '0' THEN

            next_state <= INVALID; WAIT FOR 0 NS; ELSE IF to_bit(WH) /="0" THEN
             V2V_Invalidate <= "1" ; WAIT FOR 0 NS; next_state <= "WaitUntilAllInv;" WAIT FOR 0 NS;
              ELSE next_state <= "SHARED_1;" WAIT FOR 0 NS; END IF; END IF; WHEN (B"110")>

         IF to_bit(AllInvDone) /= '0' THEN

            next_state <= MODIFIED; WAIT FOR 0 NS; ELSE next_state <= "WaitUntilAllInv;" WAIT FOR 0 NS;
             END IF; WHEN (B"010")>

         IF to_bit(SHR) /= '0' THEN

            V2V_AdrRetry <= '0'; WAIT FOR 0 NS; next_state <= "SHARED_1;" WAIT FOR 0 NS;
             ELSE IF to_bit(SHW) /="0" THEN next_state <= "INVALID;" WAIT FOR 0 NS;
              ELSE IF to_bit(WH) /="0" THEN next_state <= "MODIFIED;" WAIT FOR 0 NS;
               ELSE next_state <= "EXCLUSIVE;" WAIT FOR 0 NS; END IF; END IF; END IF; WHEN (B"011")>

         IF to_bit(SHW) /= '0' THEN

            next_state <= INVALID; WAIT FOR 0 NS; ELSE IF to_bit(SHR) /="0" THEN
             V2V_AdrRetry <= "1" ; WAIT FOR 0 NS; next_state <= "start_write_back;" WAIT FOR 0 NS;
              ELSE next_state <= "MODIFIED;" WAIT FOR 0 NS; END IF; END IF; WHEN (B"101")>

         IF to_bit(write_back_done) /= '0' THEN

            next_state <= SHARED_1; WAIT FOR 0 NS; ELSE next_state <= "start_write_back;" WAIT FOR 0 NS;
             END IF; WHEN OTHERS>

         NULL;

      END CASE;

   END IF;

END PROCESS;



PROCESS 

BEGIN

   WAIT UNTIL posedge(clk);

   present_state <= next_state; WAIT FOR 0 NS; V2V_new_state <= "next_state;" WAIT FOR 0 NS;
    END PROCESS;
     Cache_Sector_Fill <= "V2V_Cache_Sector_Fill;"
      Invalidate <= "V2V_Invalidate;" AdrRetry <= "V2V_AdrRetry;" new_state <= "V2V_new_state;"
       END VeriArch; LIBRARY ieee; USE ieee.std_logic_1164.all;
        ENTITY cache IS

GENERIC (CONSTANT CYCLE : integer := 10);

END cache;



LIBRARY Verilog;

LIBRARY Std;


ARCHITECTURE VeriArch OF cache IS

USE Verilog.functions.all;

USE Verilog.timing.all;

USE Std.textio.all;

USE Verilog.numeric_std.all;

USE Verilog.v2v_types.all;

CONSTANT v2v_message0 : string(1 TO 58) := "
Example: maintaining cache coherence in 2-processor system";

CONSTANT v2v_message1 : string(1 TO 58) := "
Example: maintaining cache coherence in 2-processor system";

CONSTANT v2v_message2 : string(1 TO 5) := "SHit ";

CONSTANT v2v_message3 : string(1 TO 7) := " Abort ";

CONSTANT v2v_message4 : string(1 TO 9) := " RD_DONE ";

CONSTANT v2v_message5 : string(1 TO 9) := " WB_DONE ";

CONSTANT v2v_message6 : string(1 TO 19) := " Cache_Sector_Fill ";

CONSTANT v2v_message7 : string(1 TO 5) := " Inv ";

CONSTANT v2v_message8 : string(1 TO 12) := " AllInvDone ";

CONSTANT v2v_message9 : string(1 TO 8) := " stateA ";

CONSTANT v2v_message10 : string(1 TO 8) := " stateB ";

CONSTANT v2v_message11 : string(1 TO 1) := " ";

CONSTANT v2v_message12 : string(1 TO 5) := "SHit ";

CONSTANT v2v_message13 : string(1 TO 7) := " Abort ";

CONSTANT v2v_message14 : string(1 TO 9) := " RD_DONE ";

CONSTANT v2v_message15 : string(1 TO 9) := " WB_DONE ";

CONSTANT v2v_message16 : string(1 TO 19) := " Cache_Sector_Fill ";

CONSTANT v2v_message17 : string(1 TO 5) := " Inv ";

CONSTANT v2v_message18 : string(1 TO 12) := " AllInvDone ";

CONSTANT v2v_message19 : string(1 TO 8) := " stateA ";

CONSTANT v2v_message20 : string(1 TO 8) := " stateB ";

SIGNAL RMS : std_logic REGISTER  := '0';

SIGNAL RME : std_logic REGISTER ;

SIGNAL WM : std_logic REGISTER  := '0';

SIGNAL WH : std_logic REGISTER  := '0';

SIGNAL RH : std_logic REGISTER ;

SIGNAL SHR : std_logic REGISTER  := '0';

SIGNAL SHW : std_logic REGISTER  := '0';

SIGNAL clk : std_logic REGISTER  := '0';

SIGNAL READ_DONE : std_logic REGISTER  := '0';

SIGNAL reset : std_logic REGISTER ;

SIGNAL send_abort : std_logic REGISTER  := '0';

SIGNAL write_back_done : std_logic REGISTER  := '0';

SIGNAL AllInvDone : std_logic REGISTER  := '0';

SIGNAL PA : std_logic REGISTER ;

SIGNAL PB : std_logic REGISTER ;

SIGNAL countE : std_logic REGISTER ;

SIGNAL state : std_logic_vector(2 DOWNTO 0) REGISTER ;

SIGNAL SectorInCacheA : std_logic_vector(2 DOWNTO 0) REGISTER  := "000";

SIGNAL SectorInCacheB : std_logic_vector(2 DOWNTO 0) REGISTER  := "000";

SIGNAL count : std_logic_vector(3 DOWNTO 0) REGISTER ;

SIGNAL file1 : v2v_integer REGISTER  := 2;

SIGNAL new_state : std_logic_vector(2 DOWNTO 0);

SIGNAL Cache_Sector_Fill : std_logic;

SIGNAL Invalidate : std_logic;

SIGNAL AdrRetry : std_logic;

SIGNAL std_io : integer := 1;

FILE F1 : text open WRITE_MODE IS "/dev/tty";

FILE F2 : text open WRITE_MODE IS "cache.list";

PROCEDURE writeline (unsigned_filechannel : IN unsigned;

                 VARIABLE l : INOUT line;

                 line_feed : IN character := LF) IS 

BEGIN

   IF unsigned_filechannel(1) = '1' THEN

      write(F1, l.all & line_feed);

   END IF;

   IF unsigned_filechannel(2) = '1' THEN

      write(F2, l.all & line_feed);

   END IF;

   Deallocate(l);

END;

PROCEDURE V2V_display (SIGNAL filechannel : IN integer;

                 message1 : IN string := "";

                 signal1 : IN bit_vector := "";

                 message2 : IN string := "";

                 signal2 : IN bit_vector := "";

                 message3 : IN string := "";

                 signal3 : IN bit_vector := "";

                 message4 : IN string := "";

                 signal4 : IN bit_vector := "";

                 message5 : IN string := "";

                 signal5 : IN bit_vector := "";

                 message6 : IN string := "";

                 signal6 : IN bit_vector := "";

                 message7 : IN string := "";

                 signal7 : IN bit_vector := "";

                 message8 : IN string := "";

                 signal8 : IN bit_vector := "";

                 message9 : IN string := "";

                 signal9 : IN bit_vector := "";

                 message10 : IN string := "";

                 signal10 : IN bit_vector := "";

                 message11 : IN string := "";

                 signal11 : IN bit_vector := "";

                 message12 : IN string := "") IS 

VARIABLE l : line;

VARIABLE unsigned_filechannel : unsigned(2 DOWNTO 1);

BEGIN

   write(l, message1, LEFT, 0);

   write(l, signal1, LEFT, 0);

   write(l, message2, LEFT, 0);

   write(l, signal2, LEFT, 0);

   write(l, message3, LEFT, 0);

   write(l, signal3, LEFT, 0);

   write(l, message4, LEFT, 0);

   write(l, signal4, LEFT, 0);

   write(l, message5, LEFT, 0);

   write(l, signal5, LEFT, 0);

   write(l, message6, LEFT, 0);

   write(l, signal6, LEFT, 0);

   write(l, message7, LEFT, 0);

   write(l, signal7, LEFT, 0);

   write(l, message8, LEFT, 0);

   write(l, signal8, LEFT, 0);

   write(l, message9, LEFT, 0);

   write(l, signal9, LEFT, 0);

   write(l, message10, LEFT, 0);

   write(l, signal10, LEFT, 0);

   write(l, message11, LEFT, 0);

   write(l, signal11, LEFT, 0);

   write(l, message12, LEFT, 0);

   unsigned_filechannel := to_unsigned(filechannel, 2);

   writeline(unsigned_filechannel, l);

END;

BEGIN



PROCESS 

BEGIN

   V2V_display(std_io, v2v_message0);

   V2V_display(file1, v2v_message1);

   state <= SectorInCacheA; WAIT FOR 0 NS; PA <= "1" ; WAIT FOR 0 NS; PB <= "0" ; WAIT FOR 0 NS;
   RME <= "1" ; WAIT FOR 0 NS; reset <= "1" ; WAIT FOR 6 NS; reset <= "0" ; WAIT FOR 40 NS;
   PA <= "0" ; WAIT FOR 0 NS; PB <= "1" ; WAIT FOR 0 NS; RME <= "0" ; WAIT FOR 0 NS;
   RMS <= "1" ; WAIT FOR 0 NS; state <= "SectorInCacheB;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 50 NS; PB <= "0" ; WAIT FOR 0 NS;
   PA <= "1" ; WAIT FOR 0 NS; SHR <= "1" ; WAIT FOR 0 NS; state <= "SectorInCacheA;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 20 NS; SHR <= "0" ; WAIT FOR 0 NS;
   WH <= "1" ; WAIT FOR 0 NS; state <= "SectorInCacheA;" WAIT FOR 0 NS; reset <= "1" ; WAIT FOR 10 NS;
   reset <= "0" ; WAIT FOR 50 NS; PA <= "0" ; WAIT FOR 0 NS; PB <= "1" ; WAIT FOR 0 NS;
   RMS <= "1" ; WAIT FOR 0 NS; WH <= "0" ; WAIT FOR 0 NS; state <= "SectorInCacheB;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 30 NS;
   SHR <= "1" ; WAIT FOR 0 NS; RMS <= "0" ; WAIT FOR 0 NS; PA <= "1" ; WAIT FOR 0 NS;
   PB <= "0" ; WAIT FOR 0 NS; state <= "SectorInCacheA;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 20 NS;
   PB <= "1" ; WAIT FOR 0 NS; PA <= "0" ; WAIT FOR 0 NS;
   SHR <= "0" ; WAIT FOR 0 NS;
   state <= "SectorInCacheB;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 20 NS;
   PB <= "0" ; WAIT FOR 0 NS; PA <= "1" ; WAIT FOR 0 NS;
   state <= "SectorInCacheA;" WAIT FOR 0 NS; reset <= "1" ; WAIT FOR 30 NS;
   write_back_done <= "1" ; WAIT FOR 10 NS; write_back_done <= "0" ; WAIT FOR 10 NS;
   PA <= "0" ; WAIT FOR 0 NS; PB <= "1" ; WAIT FOR 0 NS;
   RMS <= "1" ; WAIT FOR 0 NS; state <= "SectorInCacheB;" WAIT FOR 0 NS;
   reset <= "1" ; WAIT FOR 10 NS; reset <= "0" ; WAIT FOR 0 NS;
   WAIT; END PROCESS; PROCESS BEGIN SectorInCacheB <= "NULL;" WAIT ON new_state;
   IF PA="1" THEN SectorInCacheA <= "new_state;" WAIT FOR 0 NS;
    ELSE IF PB="1" THEN SectorInCacheB <= "new_state;" WAIT FOR 0 NS;
   SectorInCacheB <= "NULL;" END IF; END IF;
   END PROCESS;
   PROCESS BEGIN READ_DONE <= "NULL;" countE <= "NULL;" count <= "NULL;"
    SectorInCacheB <= "NULL;" WAIT UNTIL posedge(clk); IF to_bit(Invalidate) /="0" THEN WAIT FOR 10 NS;
   SectorInCacheB <= "000" ; WAIT FOR 0 NS; SectorInCacheB <= "NULL;" WAIT FOR 10 NS;
   AllInvDone <= "1" ; WAIT FOR 15 NS; AllInvDone <= "0" ; WAIT FOR 0 NS;
   ELSE IF to_bit(Cache_Sector_Fill) /="0" THEN count <= "0000" ;
   WAIT FOR 0 NS; count <= "NULL;" countE <= "1" ; WAIT FOR 0 NS;
   countE <= "NULL;" READ_DONE <= "0" ; WAIT FOR 0 NS;
   READ_DONE <= "NULL;" ELSE IF to_bit(AdrRetry) /="0" THEN countE <= "0" ; WAIT FOR 0 NS;
   countE <= "NULL;" send_abort <= "1" ; WAIT FOR 40 NS; send_abort <= "0" ; WAIT FOR 0 NS;
   END IF; END IF; END IF; END PROCESS;
   PROCESS BEGIN count <= "NULL;" countE <= "NULL;" READ_DONE <= "NULL;" WAIT UNTIL posedge(clk);
   IF READ_DONE="1" THEN READ_DONE <= "0" ; WAIT FOR 0 NS; READ_DONE <= "NULL;" END IF;
   IF countE="1" THEN IF count="0010" THEN READ_DONE <= "1" ; WAIT FOR 0 NS;
   READ_DONE <= "NULL;" countE <= "0" ; WAIT FOR 0 NS;
   countE <= "NULL;" ELSE count <= "count" + "0001"; WAIT FOR 0 NS; count <= "NULL;" END IF;
   END IF;
   V2V_display(std_io, v2v_message2, to_bitvector(SHR), v2v_message3,
    to_bitvector(send_abort), v2v_message4, to_bitvector(READ_DONE), v2v_message5,
    to_bitvector(write_back_done), v2v_message6, to_bitvector(Cache_Sector_Fill), v2v_message7,
    to_bitvector(Invalidate), v2v_message8, to_bitvector(AllInvDone), v2v_message9,
    to_bitvector(SectorInCacheA), v2v_message10, to_bitvector(SectorInCacheB));
   V2V_display(file1, INTEGER'IMAGE(now / 1 NS), OPEN, v2v_message11, OPEN, v2v_message12,
    to_bitvector(SHR), v2v_message13, to_bitvector(send_abort), v2v_message14,
    to_bitvector(READ_DONE), v2v_message15, to_bitvector(write_back_done), v2v_message16,
    to_bitvector(Cache_Sector_Fill), v2v_message17, to_bitvector(Invalidate), v2v_message18,
    to_bitvector(AllInvDone), v2v_message19, to_bitvector(SectorInCacheA), v2v_message20,
    to_bitvector(SectorInCacheB));
    END PROCESS;
    PROCESS BEGIN WAIT FOR parameter_delay(NS, CYCLE / 2); clk <= "NOT" clk; WAIT FOR 0 NS; END PROCESS;
   
   u1 : ENTITY work.cache_coherence(VeriArch)
    PORT MAP (new_state, Cache_Sector_Fill, Invalidate, AdrRetry, RMS, RME, WM, WH, SHR,
     SHW, state, READ_DONE, clk, reset, send_abort, write_back_done, AllInvDone) ;

END VeriArch;