--------------------------------------------------------------------------------
--
-- File Type:    VHDL 
-- Input Verilog file was: voter.v
-- Tool Version: verilog2vhdl  v2.2  Tue May 16 16:50:46 EDT 1995  
-- Date Created: Thu May 25 09:44:43 1995
--
--------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY voter IS
PORT (SIGNAL z_out : OUT std_logic;
      SIGNAL a : IN std_logic_vector(7 DOWNTO 0);
      SIGNAL b : IN std_logic_vector(7 DOWNTO 0);
      SIGNAL en1 : IN std_logic;
      SIGNAL en2 : IN std_logic;
      SIGNAL dummy_in : IN std_logic;
      SIGNAL dummy_out : OUT std_logic);
END voter;

LIBRARY Verilog;
ARCHITECTURE VeriArch OF voter IS
USE Verilog.functions.all;
SIGNAL V2V_z_out : std_logic REGISTER ;
SIGNAL V2V_dummy_out : std_logic;
SIGNAL GUARD : boolean := TRUE;
BEGIN

PROCESS 
BEGIN
   V2V_z_out <= NULL;
   WAIT ON a;
   IF en1 = '1' OR en2 = '1' THEN
      IF a = b THEN
         V2V_z_out <= '1';
         WAIT FOR 0 NS;
         V2V_z_out <= NULL;
      ELSE
         V2V_z_out <= '0';
         WAIT FOR 0 NS;
         V2V_z_out <= NULL;
      END IF;
   ELSE
      V2V_z_out <= 'Z';
      WAIT FOR 0 NS;
      V2V_z_out <= NULL;
   END IF;
END PROCESS;

PROCESS 
BEGIN
   V2V_z_out <= NULL;
   WAIT ON b;
   IF en1 = '1' OR en2 = '1' THEN
      IF a = b THEN
         V2V_z_out <= '1';
         WAIT FOR 0 NS;
         V2V_z_out <= NULL;
      ELSE
         V2V_z_out <= '0';
         WAIT FOR 0 NS;
         V2V_z_out <= NULL;
      END IF;
   ELSE
      V2V_z_out <= 'Z';
      WAIT FOR 0 NS;
      V2V_z_out <= NULL;
   END IF;
END PROCESS;
z_out <= V2V_z_out;
dummy_out <= V2V_dummy_out;
END VeriArch;