WaveFormer Lite is a special version of WaveFormer Pro
that can generate VHDL and Verilog stimulus-based test
benches for the Actel Libero design software and other FPGA/ASIC vendor flows. WaveFormer
Lite fits seamlessly into Actel�s design environment,
automatically extracting signal information from your HDL
design files, and producing HDL test bench code that can
be used with any standard VHDL or Verilog simulator.
WaveFormer Lite Design Flow with Actel
WaveFormer Lite generates VHDL and Verilog test benches
from drawn waveforms. There are three basic steps for
creating test benches using WaveFormer Lite and the Actel
1) Download and Install WaveFomer or other SynaptiCAD product
Go to the download page and download
the SynaptiCAD Product suite. Check the WaveFormer
Pro check box. Run the allproducts.exe to install the
software. If you already own WaveFormer Pro, DataSheet
Pro, or BugHunter Pro you can skip this step.
2) Launch WaveFormer Lite from within Libero
Follow the instructions in the Libero help on how to launch WaveFormer Lite.
WaveFormer Lite Design Flow without Libero
If you are not using Libero, then select Project > New
Project menu and add your source code files to the
list as shown in Section 4.4 Export VHDL and Verilog
test benches in the Timning Diagram Editor help.
WaveFormer Pro Upgrade Path
WaveFormer Lite licenses can be upgraded to
WaveFormer Pro which includes waveforms generated from Boolean and
Registered logic equations, min-max timing analysis, and support
for more input and export formats including Tektronix and Agilent