Press Release for Product Upgrade: November 10, 2008

SynaptiCAD offers HDL Works Tools

SynaptiCAD is now the US and Canadian distributor for HDL Works EDA tools: Ease, HDL Companion, and IO Checker. These tools provide alternative graphical approaches for VHDL and Verilog code design which also complement SynaptiCAD's timing diagram editors and graphical simulation tools. EASE provides a state machine bubble editor, truth table designer, and block diagram design environment for generating VHDL and Verilog code. HDL Companion scans design directories and creates a complete hierarchal view of any VHDL or Verilog design and supporting files that helps engineers explore unfamiliar designs. It also includes linting and HTML document generation. IO Checker verifies hundreds of pins between an FPGA and the PCB design using a rules-based approach via regular expressions.

Synergistic Products

"We've been searching for a good partner to distribute our tools in the United States and Canadian markets, and SynaptiCAD's experience with VHDL and Verilog productivity tools was just what we were looking for," said Willem Gruter, CEO of HDL Works. "We are very excited that SynaptiCAD has agreed to distribute the HDL Works product line."

Dan Notestein, president of SynaptiCAD, responded that "We've been aggressively looking to expand our portfolio of HDL design and verification tools to complement our existing products. SynaptiCAD has established a reputation for bringing to market high quality products and a level of service and support that's often absent nowadays in EDA and we plan to leverage that base further by working with other like-minded EDA companies. The HDL Works tools fill the gap we had in our line for graphically generating synthesizable HDL code."

EASE Block and State Diagram HDL Entry

EASE offers the best of both worlds with your choice of graphical or text-based HDL entry. You don't need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your preferred mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language - VHDL or Verilog. EASE supports industry standard version control environments that deal with design and configuration management, enabling multiple users to work simultaneously on one EASE project.

HDL Companion for design exploration

HDL Companion helps you explore any HDL design, including third party IP, legacy code and other HDL sources. HDL Companion scans design directories and uses the information to generate a hierarchal view of the HDL code and all supporting files. The embedded fuzzy parsers accept any Verilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems not reported by the compilers. The GUI offers many ways to navigate through the design and explore the details you're looking for including a tree browser, hierarchical chart, signal trace charts, text editors, and lint results. The GUI can also launch your simulator. HDL Companion is an excellent tool for navigating through a design and it is especially useful for investigating designs that are unfamiliar.

IO Checker verifies hundreds of pins in between FPGA and PCB

When using large FPGAs on a PCB, making sure that the FPGA pins are connected to the right PCB signals is a cumbersome task. On the FPGA side, the pins are assigned to the HDL signals that form the toplevel of the logic implemented on the FPGA. On the PCB side, the pins have to be connected to the proper net that will connect it to other components on the PCB. Because implementation of FPGA and PCB is often done in parallel, the signal names used are not always identical. To make things even worse, it is often necessary to perform pin swaps to prevent PCB routing problems. These pin swaps have to be made both on the FPGA and the PCB. As this is almost always manual work, and current devices have over 1500 pins, a mistake is easily made.

Pricing and Availability

EASE, HDL Companion, and IO Checker are available on Windows, Solaris, and Linux. The software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available. For more information, contact SynaptiCAD at phone (540)953-3390, fax (540)953-3078, email: [email protected], web

Marketing Contact

For any questions concerning this press release please contact Donna Mitchell at 540-953-3390 or email at [email protected]. High-resolution images can be downloaded directly from SynaptiCAD's web site at