TestBencher Pro generates code for OpenVera

BLACKSBURG, VA, May 25, 2001 -- SynaptiCAD Inc., the design technology leader for timing diagram editing and test bench generation, today announced the release of TestBencher Pro v7.4, which supports graphical code generation for the OpenVera(TM) hardware verification language. TestBencher Pro provides designers with a graphical environment for generating cycle-based or time-based bus-functional models from language-independent timing diagrams. Each timing diagram created by the user is converted into an equivalent OpenVera transaction by TestBencher Pro.

"We wanted to upgrade our verification flow to include the power of the new verification languages like OpenVera, but we were reluctant to incur the down time necessary to learn the language. Then we discovered TestBencher Pro's graphical verification environment and were impressed with the speed in which we could quickly develop a VERA test bench," said Cecil Stone, senior verification engineer at Lucent Technologies. "Also TestBencher Pro's language independent timing diagrams let us quickly generate Verilog test benches to perform timing tests on the same models."

"This is an exceptional opportunity for designers with large verification tasks to access the industry's most powerful verification technologies - the OpenVera language and graphical test bench generation," said Dan Notestein, president of SynaptiCAD. "OpenVera provides powerful constructs for handling sequence recognition, arbitration, comprehensive dynamic coverage analyses that are not available in VHDL or Verilog. TestBencher Pro's graphical interface allows the user to take advantage of these OpenVera features quickly and easily - without having to learn the details of the language. The graphical representation also enhances the ability of engineers to share data across projects."

"We are pleased that SynaptiCAD offers a graphical environment that leverages OpenVera, the open source hardware verification language, in the TestBencher Pro product," said Rich Goldman, vice president of strategic market development at Synopsys.

"The innovative combination of TestBencher Pro and VERA delivers a consistent and quick solution to the most demanding verification problems," said Paul Graykowski, VERA technical marketing manager at Synopsys. "This integration allows designers to focus on the verification of the device under test and not on the implementation of the test bench."

About TestBencher Pro

TestBencher Pro generates OpenVera test benches directly from timing diagrams. The test benches use a bus-functional model architecture that executes faster than complete functional models and can be created from data contained in data sheets. Additionally, TestBencher's graphical representations and automatic code generation abstract coding details away from the user. This abstraction reduces the amount of time needed for test bench generation. Automating the most tedious aspects of test bench development allows engineers to focus on the design and operation of the test bench rather than the painstaking aspects of code development. The generated test benches are compiled with the VERA(R) test bench automation tool and simulated using all major VHDL and Verilog simulators.

TestBencher Pro features state and timing protocol checker generation for verifying the response of the model being tested. TestBencher's "sampling" construct can check the state of a signal at a given point in time or over a window of time, and samples can also check for either a state change or for stability during the sampling window. Sampling window intervals can be specified as an amount of time or number of clock cycles (to support cycle-based test bench generation).

TestBencher Pro also supports various "data sources and targets" that allow the user to easily read and write data from table-formatted files, queues, arrays, and associative arrays. Data sources and targets enable storage and manipulation of complex data structures that are useful for modeling packet-based protocols. This feature is particularly useful when generating bus-functional models to test devices on a communications bus.

Other features include automatic port and signal extraction from HDL models, parameterization of both state and timing values through function call parameters or data files, checkers for signal stability and/or edge transitions within a window of time, and conditional application of edge transitions based on these checks. SynaptiCAD also offers a complete line of VHDL and Verilog model generation, simulation, and timing diagram visualization tools including: VeriLogger Pro - Verilog simulator, WaveFormer Pro - waveform translator, Timing Diagrammer Pro - timing diagram editor, and DataSheet Pro - a Data Book design tool.

Contact Information

TestBencher Pro v7.4 is currently available on Solaris/HP-UX and Windows NT starting at $15000. For more information, contact SynaptiCAD at phone (540)953-3390, fax (540)953-3078, email: Sales Office, web site: http://www.syncad.com. For questions concerning this press release, please contact Donna Mitchell at (540) 953-3390.