Next: Conditional 'if-else-if',
Main: Supported Constructs,
Previous: Always Statement
The initial statement is similar to the always statement, except that it executes only once during the
entire simulation run. It is functionally equivalent to a VHDL process with an infinite wait statement
at the end of the sequential body.
Register initialization in initial statements without event control are handled as a special case. If
the register initialization is the first statement in the initial block without event control (precedes
ALL wait statements), the statement is mapped to a signal initialization statement in VHDL.